Time sequence testing system and testing method thereof

Abstract

The invention discloses a time sequence testing system. The system comprises a testing machine, and the testing machine comprises a test vector storage unit, an information recording unit, a sampling unit and a processor unit; a tested chip is selected; the test vector storage unit is controlled by the processor unit to input an excitation signal into the tested chip; after the excitation signal is received, the tested chip outputs a response signal which is corresponding to the excitation signal and has certain time delay; multiple sampling is carried out on the response signal by the sampling unit according to a fixed sampling frequency; sampling data is stored into a designated address by the information recording unit in real time; and then the processor unit reads the sampling data in the designated address from the information recording unit, calculates delay time T and outputs a result. With the adoption of a time sequence testing method of the time sequence testing system, time sequence testing efficiency can be effectively improved and time can be saved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a timing test system and a test method thereof. Background technique [0002] At present, to ensure the correctness of VLSI design, two requirements need to be met: first, the correctness of the basic functions of the chip circuit; second, the correctness of the timing of all devices in the chip circuit. Due to the transmission of signals in the chip and the design requirements of the chip, there will be a certain delay time between the response signal of the chip and the corresponding excitation signal. If the delay time is too long or too short, it will affect the normal operation of the chip. Time for accurate detection, so as to determine whether the chip can work normally. [0003] In the prior art, the method of using a test machine to perform timing testing is mainly: after inputting an excitation signal to the chip under test, sampling the response signal of the c...

AI Technical Summary

Problems solved by technology

[0004] Due to the need for multiple signal inputs, sampling and judgment of the response signal, and constant adjustment of the sampling time, the entire test process takes a lot of time to detect the jump of the response signal level

Even if the transition of the output level is detected, it is still difficult to obtain the exact position of the rising or falling edge, and the resolution of the test is also very low.

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