Power semiconductor device structure and preparation method on passivation semiconductor contact surface
A power semiconductor, contact surface technology, applied in the direction of semiconductor/solid state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of corrosion and high process requirements, and achieve the effect of avoiding the current limiting effect
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[0032] The present invention will be further described below in conjunction with specific drawings.
[0033] Such as Figure 1 to Figure 8 As shown: taking an N-type IGBT device as an example, the present invention includes an N-drift region 1, a gate oxide layer 2, a polycrystalline gate 3, an emitter 4, a gate electrode 5, a P-type base region 6, an N+ emitter region 7, a A collector metal region 8 , a second collector metal region 9 , and a P+ collector region 10 .
[0034] Such as figure 1 , Figure 8As shown, on the cross-section of the IGBT device, the semiconductor substrate includes an N-drift region 1, and the N-drift region 1 has a front side and a back side parallel to each other; a P-type base region 6 is provided in the N-drift region 1, The P-type base region 6 extends from the front of the N-drift region 1 to the back direction, and the extension distance of the P-type base region 6 is less than the thickness of the N-drift region 1; the P-type base region 6 ...
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