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Power semiconductor device structure and preparation method on passivation semiconductor contact surface

A power semiconductor, contact surface technology, applied in the direction of semiconductor/solid state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of corrosion and high process requirements, and achieve the effect of avoiding the current limiting effect

Active Publication Date: 2015-03-18
JIANGSU R & D CENTER FOR INTERNET OF THINGS +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Since this method requires the etching of the metal on the back side, if wet etching is used, it will corrode the metal on the front side, so only dry etching can be used, which requires relatively high process requirements.

Method used

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  • Power semiconductor device structure and preparation method on passivation semiconductor contact surface
  • Power semiconductor device structure and preparation method on passivation semiconductor contact surface
  • Power semiconductor device structure and preparation method on passivation semiconductor contact surface

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Embodiment Construction

[0032] The present invention will be further described below in conjunction with specific drawings.

[0033] Such as Figure 1 to Figure 8 As shown: taking an N-type IGBT device as an example, the present invention includes an N-drift region 1, a gate oxide layer 2, a polycrystalline gate 3, an emitter 4, a gate electrode 5, a P-type base region 6, an N+ emitter region 7, a A collector metal region 8 , a second collector metal region 9 , and a P+ collector region 10 .

[0034] Such as figure 1 , Figure 8As shown, on the cross-section of the IGBT device, the semiconductor substrate includes an N-drift region 1, and the N-drift region 1 has a front side and a back side parallel to each other; a P-type base region 6 is provided in the N-drift region 1, The P-type base region 6 extends from the front of the N-drift region 1 to the back direction, and the extension distance of the P-type base region 6 is less than the thickness of the N-drift region 1; the P-type base region 6 ...

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Abstract

The invention relates to a power semiconductor device structure on a passivation semiconductor contact surface. The power semiconductor device structure comprises a first conduction type drift region, a second conduction type base region is arranged inside the first conduction type drift region, a first conduction type emitter region is arranged inside the second conduction type base region, and a gate oxide arranged in the front of the first conduction type drift region is provided with polycrystalline gates. An emitter arranged on the second conduction type base region contacts to the second conduction type base region and the first conduction type drift region arranged inside the second conduction type base region, and the gate oxide is provided with gate electrodes. The second conduction type collector region is formed on the back surface of the first conduction type drift region, a first current collection metal region is deposited on the back surface of the first conduction type drift region, and a second current collection metal region is deposited on the first current collection metal region. The power semiconductor device structure is characterized in that the first current collection metal region is a metal film formed by Se in deposited mode. The power semiconductor device structure achieves semiconductor surface passivation, and avoids current limiting effects caused by oversize self-resistance.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a power semiconductor device structure and a manufacturing method for passivating a semiconductor contact surface, and belongs to the technical field of IGBTs. Background technique [0002] IGBT is the acronym for Insulated Gate Bipolar Transistor. It is a voltage-controlled power device and is widely used as a high-voltage switch. [0003] In the conventional IGBT manufacturing process, the first is the front process, including oxidation, ion implantation, exposure, deposition and etching, etc. to form the front PN junction, gate electrode and emitter pattern; then the back thinning process and the back Ion Implantation. The back of the conventional IGBT is P-type doped, and the doping concentration on the back of some devices is very low. If the contact resistance is not done properly, the on-resistance of the device will be too large, which will aff...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/739H01L29/45H01L29/417H01L21/331H01L21/285
Inventor 徐承福朱阳军胡爱斌谈景飞卢烁今陈宏吴凯邱颖斌
Owner JIANGSU R & D CENTER FOR INTERNET OF THINGS