High-speed signal sampling and synchronizing framework and method applied to signal processing chip

A signal processing chip, high-speed signal technology, used in signal transmission systems, electrical signal transmission systems, instruments, etc., can solve the problems of multi-channel signals being unable to synchronize, high-speed signal sampling is unstable, etc., to achieve stable transmission and achieve stability. Effect

Active Publication Date: 2013-02-13
CHENGDU GANIDE TECH
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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a high-speed signal sampling system that realizes multi-channel high-speed signal sampling and synchronous outp

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  • High-speed signal sampling and synchronizing framework and method applied to signal processing chip
  • High-speed signal sampling and synchronizing framework and method applied to signal processing chip
  • High-speed signal sampling and synchronizing framework and method applied to signal processing chip

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[0026] The specific implementation of the present invention will be described in detail below in conjunction with specific examples:

[0027] See figure 1 The high-speed signal sampling and synchronization architecture applied to the signal processing chip provided by the present invention includes an adjustable delay chain module, an asynchronous FIFO module, a read control signal generation unit, an internal self-start signal generation unit, and a first counter; The input 5-channel ADC signal is sampled and synchronized.

[0028] Among them, the adjustable delay chain module is used to perform adjustable delay processing on the input ADC clock signal, so that the ADC clock and ADC data can maintain a precise phase relationship, so that a single signal can be sampled accurately and without error; The total length of the adjustable delay chain is controlled within 1 clock cycle, so that the clock can always be sampled (delayed) by adjusting the length of the delay chain under any ...

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Abstract

The invention discloses a high-speed signal sampling and synchronizing framework applied to a signal processing chip. The framework is characterized by comprising an adjustable delay chain module, an asynchronous FIFO (First In and First Out) module connected with the adjustable delay chain module, a read control signal generating unit connected with the asynchronous FIFO module, a first counter used for receiving a starting signal and starting to count, and an internal self-starting signal generating unit connected with the first counter, wherein the internal self-starting signal generating unit is connected with the asynchronous FIFO module. The framework can be used for finishing the adjustable delay processing on ADC (Analog to Digital Conversion) clock signals, performing the asynchronous writing and the synchronous reading by the asynchronous FIFO module, and realizing the stability of signal-path signal sampling and the synchronism among multiple paths of signals, so that high-speed signals can be transmitted stably and reliably.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a framework for sampling and synchronizing high-speed signals inside a signal processing chip and a method for sampling and synchronizing high-speed signals using the framework. Background technique [0002] With the rapid development of chip design technology and manufacturing technology, the processing speed inside the chip is getting faster and faster, and the main frequency of work is getting higher and higher. The amount of data that high-speed digital-to-analog conversion (ADC) chips can provide is increasing, the output rate exceeds 1GHz, and there are more and more ADCs with sampling accuracy exceeding 10bit. For such a large amount of data, how to maintain the stability of the data after it enters the signal processing chip, and how to ensure the synchronization between the data of each channel when multiple ADCs are required, has become a must in the field of hi...

Claims

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Application Information

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IPC IPC(8): H03M1/54
Inventor 吕继平陈俊宇文建澜邸晓晓吴新春
Owner CHENGDU GANIDE TECH
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