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Transistor with self-aligned silicide and manufacturing method thereof

A technology of self-aligned silicide and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., and can solve problems such as prominent influence of integrated circuits and reduction of contact resistance

Active Publication Date: 2013-02-20
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The present invention provides a transistor with self-aligned silicide and its manufacturing method, which achieves the purpose of further reducing the contact resistance and avoiding the penetration of the source-drain junction, so as to solve the above-mentioned problem that the contact resistance has a prominent influence on the integrated circuit in the high-level integrated circuit technical questions

Method used

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  • Transistor with self-aligned silicide and manufacturing method thereof
  • Transistor with self-aligned silicide and manufacturing method thereof
  • Transistor with self-aligned silicide and manufacturing method thereof

Examples

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Embodiment 1

[0057] Such as figure 2 As shown, the transistor 200 with salicide in this embodiment includes: a substrate 201, a gate structure 202 formed on the substrate, and substrates 201 formed on both sides of the gate structure 202 The source-drain region 203 in the source-drain region 203, the first salicide layer 204 formed on the source-drain region 203, and the metal nitride layer formed on the first salicide layer 204 are sequentially stacked. layer 205 and metal layer 206 , and a second salicide layer 207 formed on the gate structure 202 . Wherein, the metal nitride layer 205 and the metal layer 206 are separated from the gate structure.

[0058] Combine below Figure 2 to Figure 9 The manufacturing process of the salicide transistor 200 of this embodiment will be described in detail.

[0059] First, if image 3 As shown, a substrate 201 is provided, and a gate structure 202 is formed on the substrate 201 . Optionally, the substrate 201 is a silicon substrate, and the gat...

Embodiment 2

[0069] The structure of the transistor with salicide in this embodiment is the same as that of the transistor with salicide in the first embodiment, and will not be repeated here.

[0070] The difference between this embodiment and Embodiment 1 is that the initial metal layer is formed before the first annealing, and the metal nitride layer and the metal layer are both formed after the first annealing.

[0071] Combine below Figure 10 to Figure 15 The manufacturing process of the salicide transistor 300 of this embodiment will be described in detail.

[0072] Such as Figure 10 As shown, first, a substrate 301 is provided, and a gate structure 302 is formed on the substrate 301 . Next, source and drain regions 303 are formed in the substrate 301 on both sides of the gate structure 302 .

[0073] Next, if Figure 11 As shown, an initial metal layer is formed on the surface of the substrate 301 and the surface of the gate structure 302 . The substrate 301 is annealed for t...

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Abstract

The invention provides a transistor with self-aligned silicide and a manufacturing method of the transistor. The transistor with the self-aligned silicide comprises a substrate, a gate structure formed on the substrate, a source drain area formed in the substrate at the two sides of the gate structure, a first self-aligned metal silicide layer formed on the source drain area, and a metal nitride layer and a metal layer which are formed on the self-aligned metal silicide layer and are sequentially overlapped, wherein the metal nitride layer and the metal layer are separated from the gate structure; and the transistor with the self-aligned silicide also comprises a second self-aligned polycrystal metal silicide layer formed on the gate structure. The transistor with the self-aligned silicide realizes the aims of further reducing the contact resistance and preventing a source drain junction from being passed through.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a self-aligned silicide transistor and a manufacturing method thereof. Background technique [0002] At present, most integrated circuits integrate multiple transistors, and multiple transistors are interconnected to complete a certain function. When the transistor is connected to other components, the contact resistance of the transistor will affect the operation effect of the entire integrated circuit. [0003] In order to reduce the contact resistance, a self-aligned silicide (SALICIDE) transistor is often used. In the salicide formation process, it is first necessary to deposit a metal layer (usually Ti, cobalt or Ni) on the polysilicon by sputtering after the gate etching and source and drain implantation are completed, and then The first rapid heating and annealing treatment (RTA) is carried out to make the polysilicon surface react with the deposited metal to fo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/45H01L21/336H01L21/28
Inventor 李乐
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP