[0021] Such as figure 1 Shown is the structure diagram of the 8b/10b encoding circuit based on rd+ in the embodiment of the present invention. The 8b/10b encoding circuit based on rd+ in the embodiment of the present invention consists of 5b/6b encoder (enc_5b_to_6b) 101 based on rd+, 3b/4b encoder (enc_3b_to_4b) 102, 5b post-processing module (post_5b) 103, 3b based on rd+ The processing module (post_3b) 104, the data merge module (data_merge) 105, the first exclusive OR module (xor1) 106 and the second exclusive OR module (xor2) 107 are constituted.
[0022] The 5b/6b encoder 101 based on rd+ is a 5b/6b encoder implemented based on the rd+ encoding method; the 3b/4b encoder 102 based on rd+ is a 3b/4b encoder implemented based on the rd+ encoding method.
[0023] The external input data is 8-bit data. The 8-bit data is split into low 5-bit data and high 3-bit data. The low 5-bit data is input to the rd+-based 5b/6b encoder 101, and the high 3-bit data is The data is input to the 3b/4b encoder 102 based on rd+. The external input data, that is, the 8-bit data includes two types of data characters and control characters. In this embodiment, the external input data is a data character, and it is assumed that the data character is D23.3, which corresponds to D23.3 The 8-bit data is 8'b0111_0111, and the corresponding low 5-bit data din[4:0] is 5'b1_0111, and the high 3-bit data din[7:5] is 3'b011. It is assumed that the polarity of the external input data, that is, the current character polarity signal crd is rd+.
[0024] An indicator signal (symbol) is used to indicate whether the 8-bit data inputted externally is a data character or a control character. The indicator signal is input to the rd+-based 5b/6b encoder 101 and the rd+-based The 3b/4b encoder 102 is used to control the encoding of the rd+-based 5b/6b encoder 101 and the rd+-based 3b/4b encoder 102. If the 8-bit data is a data character, the 5b/6b encoder 101 based on rd+ performs 5b/6b encoding according to the rd+ encoding rule of the data character, and the 3b/4b encoder 102 based on rd+ performs according to the data character rd+ encoding rules to perform 3b/4b encoding; if the 8-bit data is a control character, the 5b/6b encoder 101 based on rd+ performs 5b/6b encoding according to the rd+ encoding rule of the control character. The 3b/4b encoder 102 performs 3b/4b encoding according to the rd+ encoding rule of the control character.
[0025] Since the 8-bit data in the embodiment of the present invention is a data character, the 5b/6b encoder 101 based on rd+ in the embodiment of the present invention performs 5b/6b encoding according to the rd+ encoding rule of the data character, that is, the The lower 5-bit data din[4:0], that is, 5'b1_0111 is encoded in 5b/6b according to the rd+ encoding rule of the data character, and the encoding result is 6'b10_1000, that is, 6'b10_1000 is used as the first encoded data enc_5b[5: 0] output; meanwhile, the polarity of the 5b/6b encoder based on rd+ changes during the encoding process, and the change is represented by the first polarity change indicator signal rd_flag_5b and output.
[0026] The rd+-based 3b/4b encoder 102 performs 3b/4b encoding according to the rd+ encoding rule of the data character, that is, the high 3-bit data din[7:5], that is, 3'b011 according to the rd+ encoding rule of the data character To perform 3b/4b encoding, the encoding result is 4'b1100, that is, 4'b1100 is output as the second encoded data enc_3b[3:0]; at the same time, the polarity of the rd+-based 3b/4b encoder in the encoding process It also changes, and the change is represented by the second polarity change flag signal rd_flag_3b and output.
[0027] The first encoded data enc_5b[5:0] is input to the 5b post-processing module 103, and the 5b post-processing module 103 changes the first polarity indicator signal rd_flag_5b and the externally input current character polarity The first encoded data enc_5b[5:0] is post-processed under the control of the sex signal crd; the 5b post-processing module 103 outputs a 6-bit first post-encoded data dpost_5b[5:0] after processing. If the first polarity change indicator signal rd_flag_5b indicates that the polarity of the rd+-based 5b/6b encoder 101 changes during the encoding process, and the current character polarity signal crd is different from the rd+-based 5b When the polarity used by the /6b encoder 101 in the encoding process is not the same, the 5b post-processing module 103 inverts all the bits of the first encoded data enc_5b[5:0] bit by bit and generates the first One post-encoded data dpost_5b[5:0]; under other conditions, the 5b post-processing module 103 does not process the first encoded data enc_5b[5:0], but directly processes the first post-encoded data dpost_5b [5:0] is taken as the first encoded data enc_5b[5:0].
[0028] In the embodiment of the present invention, the first polarity change flag signal rd_flag_5b indicates that the polarity of the rd+-based 5b/6b encoder 101 has changed during the encoding process; but the current character polarity signal crd The polarity used by the 5b/6b encoder 101 based on rd+ in the encoding process is also rd+ (that is, the coding rule based on rd+ is used), so the two polarities are the same. Therefore, the 5b post-processing module 103 does not process the first encoded data enc_5b[5:0], but directly takes the first post-encoded data dpost_5b[5:0] as the first encoded data enc_5b[5:0] is 6'b10_1000.
[0029] The first XOR module 106 is configured to perform XOR processing on the first polarity change indicator signal rd_flag_5b and the current character polarity signal crd and generate the second character polarity signal enc_rd. In the embodiment of the present invention, since the polarity of the rd+-based 5b/6b encoder 101 has changed during the encoding process, the first polarity change indicator signal rd_flag_5b is 1, and the second character The polarity signal enc_rd is different from the current character polarity signal crd, and finally the second character polarity signal enc_rd is rd-.
[0030] The second XOR module 107 is configured to perform XOR processing on the second polarity change indicator signal rd_flag_3b and the second character polarity signal enc_rd to generate the next character polarity signal nrd and then One character polarity signal nrd is externally output. In the embodiment of the present invention, since the polarity of the rd+-based 3b/4b encoder changes during the encoding process, the second polarity change indicator signal rd_flag_3b is 1, so the next character polarity signal nrd is The polarity is opposite to the polarity of the second character polarity signal enc_rd, and finally the next character polarity signal nrd is rd+.
[0031] The second encoded data enc_3b[3:0] is input to the 3b post-processing module 104, and the 3b post-processing module 104 determines whether the second polarity change indicator signal rd_flag_3b and the second character polarity signal enc_rd The second encoded data enc_3b[3:0] is post-processed under control; the 3b post-processing module 104 outputs a 4-bit second post-encoded data dpost_3b[3:0] after processing. If the second polarity change indicator signal rd_flag_3b indicates that the polarity of the rd+-based 3b/4b encoder 102 changes during the encoding process, and the second character polarity signal enc_rd and the rd+-based When the polarity used by the 3b/4b encoder 102 in the encoding process is not the same, the 3b post-processing module 104 inverts all bits of the second encoded data enc_3b[3:0] bit by bit and generates the The second post-encoded data dpost_3b[3:0]; under other conditions, the 3b post-processing module 104 does not process the second encoded data enc_3b[3:0], but directly processes the second post-encoded data dpost_3b[3:0] is taken as the second encoded data enc_3b[3:0].
[0032] In the embodiment of the present invention, the second polarity change flag signal rd_flag_3b indicates that the polarity of the rd+-based 3b/4b encoder 102 has changed during the encoding process; and the second character polarity signal The polarity of enc_rd is rd-, and the polarity used by the 3b/4b encoder 102 based on rd+ in the encoding process is rd+ (that is, the encoding rule based on rd+ is used), so the two polarities are different. Therefore, finally the 3b post-processing module 104 inverts all the bits of the second encoded data enc_3b[3:0] bit by bit and generates the second post-encoded data dpost_3b[3:0]; The second post-encoded data dpost_3b[3:0] is 4'b0011.
[0033] The first post-encoded data dpost_5b[5:0] and the second post-encoded data dpost_3b[3:0] are both sent to the data merging module 105 for data merging and outputting a merged 10-bit Output data dout[9:0]. The data merging module 105 merges the first post-encoded data dpost_5b[5:0] as the lower 6 bits and the second post-encoded data dpost_3b[3:0] as the upper 4 bits, and generates a 10 Bit-wide output data. In the embodiment of the present invention, the output data dout[9:0] obtained after the merging process is 10'b00_1110_1000.
[0034] The present invention has been described in detail through specific embodiments above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can make many modifications and improvements, which should also be regarded as the protection scope of the present invention.
