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Error message recording method and redundancy substituting method for memory

A technology of error information and recording method, applied in static memory, instruments, etc., to improve reliability, avoid overflow problems, and reduce data volume

Inactive Publication Date: 2013-04-03
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The problem solved by the present invention is to propose a new memory error information recording method and a redundant replacement method to solve the overflow problem of the existing unit for recording memory test results and improve the reliability of the memory

Method used

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  • Error message recording method and redundancy substituting method for memory
  • Error message recording method and redundancy substituting method for memory
  • Error message recording method and redundancy substituting method for memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] figure 1 Shown is a flow chart of the error information recording method of the memory provided by this embodiment. figure 2 , image 3 and Figure 4 It is a structural schematic diagram of the memory, the redundant unit, and the error information register provided by this embodiment, respectively.

[0041] to combine Figure 1 to Figure 3 As shown, step S11 is executed: divide the memory 1 into regions, and the number of subunits in each region A is equal to the number of subunits in the redundant unit 2 .

[0042] Specifically, such as image 3 As shown, the redundant unit 2 has a capacity of 1M, a total of 128 rows and 8 columns. In other words, the redundant unit 2 has a 128byte subunit, or a 1024bit subunit.

[0043] Such as figure 2 As shown, the memory 1, such as but not limited to flash memory, has n sectors (sectors) from sector 0 to sector n-1, each sector is 1024 bits, 128 rows and 8 columns in total. Each bit corresponds to a storage unit, such as ...

Embodiment 2

[0053] The error information recording method and redundancy replacement method of the memory provided in the second embodiment are substantially the same as those in the first embodiment. The difference lies in that unlike the first embodiment, which stores the test result of one sector as a unit, this embodiment uses several sectors as a unit.

[0054] The memory still adopts the memory 1 with n sectors (sectors) in Embodiment 1, each sector is 1024 bits, a total of 128 rows, and 8 columns of memory 1, and the redundant unit adopts a redundant unit with a capacity of 2M, and the following is 2 The test result (error information) of the sector is stored as an example to illustrate.

[0055] In this embodiment, step S11 is executed: divide the memory 1 into regions, and the number of subunits in each region A is equal to the number of subunits in the redundant unit 2 . Specifically, such as Figure 5 As shown, every two adjacent (not limited to adjacent in other embodiments)...

Embodiment 3

[0063] The error information recording method and redundancy replacement method of the memory provided in the third embodiment are substantially the same as those in the first embodiment. The difference is that, unlike the first embodiment, which stores the test results of one sector as a unit, this embodiment uses a row of storage units (such as transistors) of the memory 1 as a unit.

[0064] The memory still adopts the memory 1 with n sectors (sectors) in the first embodiment, each sector is 1024 bits, a total of 128 rows, and 8 columns memory 1, and the redundant unit adopts a redundant unit with a capacity of 8 bits (1 byte). The test result (error information) of the storage unit of 1 row is stored as an example for an example.

[0065] In this embodiment, step S11 is executed: divide the memory 1 into regions, and the number of subunits in each region A is equal to the number of subunits in the redundant unit 2 . Specifically, such as Figure 6 As shown, each row of m...

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Abstract

The invention discloses an error message recording method and a redundancy substituting method for a memory. The error message recording method comprises the steps that the memory is subjected to area partition; the number of subcells of each area is equal to that of each redundancy cell; all the subcells in each area are subjected to performance tests; if performances of all the subcells in the area are qualified, qualification is stored in an error message recording cell; and if the performances of all the subcells in the area are disqualified, disqualification is stored in the error message recording cell. In other words, the error message recording method adopts the redundancy cells as units to record test results, and utilizes the characteristic that the redundancy cells are adopted to overall substitute multiple cells containing defect cells in the memory in a redundancy technology; data sizes of the test results are reduced; the overflow problem due to insufficient memory capacity is solved; the reliability of the memory is improved; and with the adoption of the technical scheme, a recording cell with fixed capacity can test a memory with larger capacity.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a memory error information recording method and a redundancy replacement method. Background technique [0002] As the integration level of memory, such as flash memory (Flash), continues to increase, and the storage capacity continues to increase, in the semiconductor process, it is inevitable that a certain memory unit, such as a certain transistor, has a defect. In view of the above problems, in order to improve the yield of chips, redundancy technology is generally adopted in the industry to solve them. The so-called redundant technology refers to opening up some other areas on the semiconductor, which have some spare storage units, and use the spare storage units to replace defective storage units. The above-mentioned spare storage units are also called redundant units. [0003] In redundancy technology, an essential link is to record defective units. In the prior...

Claims

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Application Information

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IPC IPC(8): G11C29/24
Inventor 吴玮
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP