Error message recording method and redundancy substituting method for memory
A technology of error information and recording method, applied in static memory, instruments, etc., to improve reliability, avoid overflow problems, and reduce data volume
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Embodiment 1
[0040] figure 1 Shown is a flow chart of the error information recording method of the memory provided by this embodiment. figure 2 , image 3 and Figure 4 It is a structural schematic diagram of the memory, the redundant unit, and the error information register provided by this embodiment, respectively.
[0041] to combine Figure 1 to Figure 3 As shown, step S11 is executed: divide the memory 1 into regions, and the number of subunits in each region A is equal to the number of subunits in the redundant unit 2 .
[0042] Specifically, such as image 3 As shown, the redundant unit 2 has a capacity of 1M, a total of 128 rows and 8 columns. In other words, the redundant unit 2 has a 128byte subunit, or a 1024bit subunit.
[0043] Such as figure 2 As shown, the memory 1, such as but not limited to flash memory, has n sectors (sectors) from sector 0 to sector n-1, each sector is 1024 bits, 128 rows and 8 columns in total. Each bit corresponds to a storage unit, such as ...
Embodiment 2
[0053] The error information recording method and redundancy replacement method of the memory provided in the second embodiment are substantially the same as those in the first embodiment. The difference lies in that unlike the first embodiment, which stores the test result of one sector as a unit, this embodiment uses several sectors as a unit.
[0054] The memory still adopts the memory 1 with n sectors (sectors) in Embodiment 1, each sector is 1024 bits, a total of 128 rows, and 8 columns of memory 1, and the redundant unit adopts a redundant unit with a capacity of 2M, and the following is 2 The test result (error information) of the sector is stored as an example to illustrate.
[0055] In this embodiment, step S11 is executed: divide the memory 1 into regions, and the number of subunits in each region A is equal to the number of subunits in the redundant unit 2 . Specifically, such as Figure 5 As shown, every two adjacent (not limited to adjacent in other embodiments)...
Embodiment 3
[0063] The error information recording method and redundancy replacement method of the memory provided in the third embodiment are substantially the same as those in the first embodiment. The difference is that, unlike the first embodiment, which stores the test results of one sector as a unit, this embodiment uses a row of storage units (such as transistors) of the memory 1 as a unit.
[0064] The memory still adopts the memory 1 with n sectors (sectors) in the first embodiment, each sector is 1024 bits, a total of 128 rows, and 8 columns memory 1, and the redundant unit adopts a redundant unit with a capacity of 8 bits (1 byte). The test result (error information) of the storage unit of 1 row is stored as an example for an example.
[0065] In this embodiment, step S11 is executed: divide the memory 1 into regions, and the number of subunits in each region A is equal to the number of subunits in the redundant unit 2 . Specifically, such as Figure 6 As shown, each row of m...
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