Multi-interrupt balance management method implemented in FPGA (field programmable gate array)

Abstract

A multi-interrupt balance management method implemented in an FPGA (field programmable gate array) is implemented by means of collaboration of several unit circuits. The unit circuits include an interrupt detection unit, an interrupt message queue, an interrupt response processing unit, a bus switch and a data buffer, wherein the interrupt detection unit is used for completing detection of external interrupt signals and latching of channel numbers; the interrupt message queue is used for storing external interrupt channel numbers and guaranteeing to respond to interrupts according to the principle of coming first and processing first; the interrupt response processing unit is responsible for executing specific interrupt tasks; the bus switch is responsible for connecting a bus of the interrupt response processing unit with a responded channel bus; and the data buffer is used for storing data read from an external bus when the interrupt response processing unit executes the interrupt processing tasks. By the method, multiple external interrupts with the same priority level can be processed timely, so that data errors or system faults caused by interrupt response imbalance are avoided.

Description

technical field [0001] The invention relates to a multi-interrupt equalization management method realized in FPGA. Background technique [0002] FPGA is also called Field Programmable Gate Array. It is a programmable logic device that emerged as a semi-custom circuit in the field of application-specific integrated circuits. The invention not only solves the deficiency of custom-made circuits, but also overcomes the disadvantage of limited gate circuits of original programmable devices. FPGA has the obvious advantages of repeatable design modification and fast operation speed. It generally uses a hardware description language (verilog or VHDL) to complete the circuit design, and forms a binary file through the synthesis and layout of special tools. After the produced binary file is burnt to the FPGA, it can run automatically when it is powered on. [0003] Because FPGA adopts the method of software programming to realize the hardware circuit design, it is very flexible to...

AI Technical Summary

Problems solved by technology

This method is stable and reliable, but it is not suitable for some systems that need to respond to external events in a timely manner. External interrupts may not be processed in time due to unbalanced interrupt processing, resulting in external data loss or system failure.

Images