FPGA data managing system

Abstract

The invention relates to an FPGA data managing system which comprises an interrupt detection unit, an interrupt message queue, an interrupt response processing unit, a bus switch and a data cache zone. An FPGA is externally connected with multiple paths of AD converters. The interrupt detection unit completes detection of external interrupt signals and latch of channel numbers. The interrupt message queue is used for storing external interrupt channel numbers and responds according to the principle of first come, first process. The interrupt response processing unit is responsible for executing specific interrupt tasks. The bus switch is responsible for connecting a bus of the interrupt response processing unit and a responded channel bus. The data cache zone is used for storing data read from an external bus when the interrupt response processing unit executes the interrupt processing tasks. According to the FPGA data managing system, multiple peripheral interrupts of the same prior level can be processed in time and data errors or system faults caused by imbalance interrupt response are avoided.

Description

technical field [0001] The invention relates to an FPGA data management system. Background technique [0002] FPGA is also called Field Programmable Gate Array. It is a programmable logic device that emerged as a semi-custom circuit in the field of application-specific integrated circuits. The invention not only solves the deficiency of custom-made circuits, but also overcomes the disadvantage of limited gate circuits of original programmable devices. FPGA has the obvious advantages of repeatable design modification and fast operation speed. It generally uses a hardware description language (verilog or VHDL) to complete the circuit design, and forms a binary file through the synthesis and layout of special tools. After the produced binary file is burnt to the FPGA, it can run automatically when it is powered on. [0003] Because FPGA adopts the method of software programming to realize the hardware circuit design, it is very flexible to use FPGA to design the circuit. F...

AI Technical Summary

Problems solved by technology

This method is stable and reliable, but it is not suitable for some systems that need to respond to external events in a timely manner. External interrupts may not be processed in time due to unbalanced interrupt processing, resulting in external data loss or system failure.

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