Electronic device and method of making the same
A technology for electronic devices and plating methods, applied in the fields of electrical solid-state devices, semiconductor/solid-state device manufacturing, electrical components, etc., which can solve the problems of increased interconnection structure cost, easy separation or detachment of interconnection patterns, waste of resources, etc.
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no. 1 approach
[0090] The following will refer to Figure 4A to Figure 4H A cross-sectional view of the first embodiment is described.
[0091] refer to Figure 4A , an insulating film 42 made of, for example, resin or silicon oxide is formed on a substrate 41 made of, for example, resin, glass, or silicon. First interconnect trenches 42A having an aspect ratio of 1 / 5 or less are formed in the first region A of the insulating film 42 . width ratio of the second interconnect trench 42B.
[0092] For example, the first interconnect trench 42A has a depth of 1 μm, a width of 5 μm, and an aspect ratio of 1 / 5. For example, the second interconnection trenches 42B each have a depth of 1 μm and a width of 1 μm, and are arranged at a pitch of 2.0 μm to form a line-space pattern in the second region B. As shown in FIG.
[0093] exist Figure 4A In this illustrated embodiment, the width (length along the arrangement direction of the channels) of the second region B is 200 μm. The length of each of ...
no. 2 approach
[0117] The following will refer to Figures 5A to 5G A cross-sectional view of the second embodiment is described.
[0118] refer to Figure 5A , an insulating film 62 made of, for example, resin or silicon oxide is formed on a substrate 61 made of, for example, resin, glass, or silicon. The first interconnect trenches 62A having an aspect ratio of 1 / 5 or less are formed in the first region A of the insulating film 62, and the first interconnect trenches 62A each having a depth exceeding 1 / 5 are formed in the second region B of the insulating film 62. width ratio of the second interconnect trench 62B.
[0119] For example, the first interconnect trench 62A has a depth of 1 μm, a width of 7 μm, and an aspect ratio of 1 / 7. For example, the second interconnection trenches 62B in the region B each have a depth of 0.5 μm and a width of 0.5 μm, and are arranged at a pitch of 0.5 μm to form a line-space pattern.
[0120] exist Figure 5A In this illustrated embodiment, the width...
Embodiment
[0139] In each case of Example 1A and Example 1B corresponding to the first embodiment, Example 2 corresponding to the second embodiment, and a comparative example corresponding to the process shown in FIGS. 1A to 1D , the actual implementation Cu layer electroplating and chemical mechanical polishing. The thickness of the Cu layer in the field section and the amount of underplating were measured before performing chemical mechanical polishing. In addition, the amount of dishing was measured after performing chemical mechanical polishing. The measurement results will be described below.
[0140] Here, the field denoted in Figure 6A The flat part shown in . For example, in Figure 4A to Figure 4N In the case of the illustrated embodiment, the field portion means a flat portion of the insulating film 42 located between the first interconnect trench 42A and the second interconnect trench 42B. The amount of underplating indicates the depth of the recess formed on the surface...
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