A method of manufacturing a semiconductor device

Abstract

The invention provides a semiconductor device manufacturing method which comprises that a semiconductor substrate is provided, a grid structure is formed on the semiconductor substrate; a first dielectric layer is formed on the semiconductor substrate and at least covers the grid structure; the first dielectric layer is ground, the top portion of the grid structure is exposed; a first metal layer is deposited and at least covers the top portion of the grid structure, and a first annealing process is carried out; the first metal layer and the first dielectric layer are removed; a second dielectric layer is formed on the semiconductor substrate and at least covers the grid structure; the second dielectric layer is etched, and a source / leakage zone of the semiconductor substrate and the grid structure are exposed; a second metal layer is deposited, and a second annealing process is carried out; the second metal layer and the second dielectric layer are removed, and a third annealing process is carried out. According to the semiconductor device manufacturing method, self-aligning silicide of a grid and the source / leakage zone can be respectively formed independently, the thicknesses of the two pieces of silicide are different, and meanwhile Ni containing Pt of different proportions is used as metal materials for the self-aligning silicide, and the electrical property of the self-aligning silicide is improved.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for forming dual self-aligned silicide (dualsalicide). Background technique [0002] With the continuous development of CMOS manufacturing technology, it is required to form ultra-shallow junctions in integrated circuits in order to minimize junction leakage, which leads to the reduction of source / drain silicide thickness when forming self-aligned silicide, thus, The thickness of the gate silicide is also reduced, resulting in a continuous increase in sheet resistance (Rs) and a decrease in device performance. [0003] For conventional salicide formation processes, the above-mentioned problems are inherent, because unless metal materials are used to form the gate, for gates formed with other materials (such as polysilicon gates), the gate salicide The salicide is formed simultaneously with the source / drain region. [0004] Therefore, it is necessary to propose a...

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Problems solved by technology

[0002] With the continuous development of CMOS manufacturing technology, it is required to form ultra-shallow junctions in integrated circuits in order to minimize junction leakage, which leads to the reduction of source / drain silicide thickness when forming self-aligned silicide, thus, The thickness of the gate silicide is also reduced, resulting in a continuous increase in sheet resistance (Rs) and a decrease in device performance

[0003] For conventional salicide formation processes, the above-mentioned problems are inherent, because unless metal materials are used to form the gate, for gates formed with other materials (such as polysilicon gates), the gate salicide Simultaneously formed with source / drain salicide

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