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Method for reducing chip edge photoresistance slope region

A technology of edge light and edge exposure, used in microlithography exposure equipment, photolithographic process exposure devices, electrical components, etc.

Inactive Publication Date: 2013-05-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a method for reducing the photoresist slope area on the edge of the chip, which can solve the problem of pinhole-like defects on the edge of the chip

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  • Method for reducing chip edge photoresistance slope region
  • Method for reducing chip edge photoresistance slope region

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Experimental program
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Embodiment Construction

[0030] Such as figure 1 As shown, the present invention reduces the method for chip edge photoresist slope area, comprises the following steps:

[0031] The first step is to form the first layer of photoresist 2;

[0032] Process 1. Firstly, use HMDS (hexamethyldisilazane) for pretreatment, and then coat the first layer of photoresist 2 on the bottom layer 1, so that the thickness of the first layer of photoresist 2 can block etching; The existing technology performs soft baking (Soft Baking), and then uses EBR (edge ​​photoresist removal method) to wash the edge of the chip;

[0033] Step 2: Carry out the first chip edge exposure (WEE), and the exposure width is a;

[0034] The second step is to form a second layer of photoresist 3;

[0035] Process 1. No solvent is used, that is, non-RRC (Reduce Resist Coating) method (no solvent is sprayed during the coating process), and the second layer of photoresist 3 is coated on the first layer of photoresist 2; then the existing t...

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Abstract

The invention discloses a method for reducing chip edge photoresistance slope region, comprising the following steps: first, forming a first photoresist layer; second, forming a second photoresist layer; third, exposing the chip; and fourth, postbaking, developing and hard baking in turn. According to the invention, by twice gluing, the exposed area of the chip edges is controlled respectively in the process of twice gluing, so that the exposure area of the chip edge for the second time is smaller than that of the first time. The edge exposure slope of the second gluing is used as the hard film of the first chip edge exposure area for developing, so as to form a desired pattern.

Description

technical field [0001] The invention relates to a semiconductor photolithography process method, in particular to a method for reducing the photoresist slope area at the edge of a chip. Background technique [0002] During the semiconductor photolithography process, due to the edge effect, the thickness of the photoresist at the edge of the chip will be abnormal. In order to remove the photoresist at the wafer edge, it is necessary to control the photoresist slope at the wafer edge. [0003] There are two existing ways to control the photoresist slope at the edge of the chip: EBR (Edge Bead Removal, edge photoresist removal method) and WEE (Wafer Edge Exposure, chip edge exposure). But both approaches have obvious disadvantages. EBR has the problem of residual areas, and it is difficult to clean; in addition, the profile of EBR itself is not very good. However, WEE uses mechanical light blocking instead of lens (Lens) imaging in the operation process, the angle is extreme...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F7/20H01L21/312
Inventor 丁刘胜
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP