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Technique method of manufacturing groove metal oxide semiconductor (MOS)

A process method and trench technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of inaccurate relative position control of epitaxy and trench, difficult device performance, etc., and achieve optimal breakdown voltage and The effect of on-state resistance

Inactive Publication Date: 2013-05-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When two layers of epitaxy are required, the existing technological process is not precise enough to control the relative position of the epitaxy and the trench, thus making it difficult to optimize epitaxy doping and device performance

Method used

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  • Technique method of manufacturing groove metal oxide semiconductor (MOS)
  • Technique method of manufacturing groove metal oxide semiconductor (MOS)
  • Technique method of manufacturing groove metal oxide semiconductor (MOS)

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Embodiment Construction

[0018] The present invention makes the technological method of trench MOS, comprises the following steps:

[0019] first step, such as figure 1 As shown, the epitaxial layer is grown on the heavily doped silicon substrate to form the first lightly doped epitaxial layer; the concentration of the heavily doped body is 10 18 / cm 3 above;

[0020] The second step, such as figure 1 As shown, silicon dioxide is grown on the first lightly doped epitaxial layer, and its thickness is equal to or greater than the depth of the trench to be formed subsequently;

[0021] The third step, such as figure 2 As shown, the photolithography process is used to apply glue and photolithography on the silicon dioxide to form a photoresist pattern;

[0022] The fourth step, such as image 3 As shown, etching, the silicon dioxide that is not blocked by the photoresist is etched away, exposing the first lightly doped epitaxial layer other than the photoresist; then the photoresist is removed; ...

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PUM

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Abstract

The invention discloses a technique method of manufacturing a groove metal oxide semiconductor (MOS). The technique method of manufacturing the groove MOS comprises the following steps. The first step is that an epitaxial layer grows on a heavily-doped silicon substrate, and a first lightly-doped epitaxial layer is formed; the second step is that silicon dioxide grows on the first lightly-doped epitaxial layer; the third step is that a photoresist pattern is formed on the silicon dioxide; the fourth step is that the silicon dioxide which is unblocked by photoresist is etched cleanly, so that the first lightly-doped epitaxial layer except the photoresist is exposed, and then the photoresist is eliminated; the fifth step is that a second epitaxial layer grows selectively, a second lightly-doped epitaxial layer grows on the surface of the exposed first lightly-doped epitaxial layer, and yet the silicon dioxide does not grow; the sixth step is the silicon dioxide is etched away through a wet process, and a groove is formed. According to the technique method of manufacturing the groove MOS, selectively epitaxial growth is adopted to form the groove, the position of an epitaxial layer of a double-layer epitaxial groove MOS relative to the groove can be controlled accurately, and thereby the breakdown voltage and the on-state resistance of a device are enabled to be optimized by respectively controlling the dosage concentration of the two layers of epitaxy.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a trench MOS. Background technique [0002] The existing trench MOS (Metal Oxide Semiconductor) process forms trenches by etching, and generally there is only one layer of epitaxy on heavily doped. When two layers of epitaxy are required, the relative position control of the epitaxy and the trench is not precise enough in the existing technical process, thus making it difficult to optimize epitaxy doping and device performance. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a process method for making trench MOS, which can accurately control the position of the epitaxial layer of the double-layer epitaxial trench MOS relative to the trench. [0004] In order to solve the above-mentioned technical problems, the technical solution of the process method of making trench MOS...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
Inventor 金勤海曹俊王军明
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP