Fin field effect transistors and methods for fabricating the same

Abstract

The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.

Description

technical field [0001] The present invention relates to integrated circuit fabrication, and more particularly, to fin field effect transistors. Background technique [0002] As the semiconductor industry has advanced to nanotechnology process nodes in pursuit of greater device density, superior performance, and lower cost, challenges in manufacturing and design issues have given rise to three-dimensional designs such as fin field-effect transistors (FinFETs). )development of. A typical FinFET is fabricated with vertical thin "fins" (or fin structures) extending from the substrate, eg, etched into the silicon layer of the substrate. In this vertical fin the channel of the FinFET is formed. A gate is provided over (eg surrounding) three sides of the fin. Having gates on both sides of the channel allows the trench to be gate controlled from both sides. Furthermore, carrier mobility can be enhanced using strained material in the recessed source / drain (S / D) portions of FinFET...

AI Technical Summary

Problems solved by technology

[0003] However, challenges remain in applying such components and processes in complementary metal-oxide-semiconductor (CMOS) fabrication

For example, flexible circuit design is difficult to achieve using FinFETs since it is feasible for FinFET fabrication to form FinFETs from multiple identical fins

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