A column-interleaved SRAM architecture for subthreshold operation

Abstract

The invention discloses an array-interleave static random access memory (SRAM) structure capable of achieving subthreshold working. The array-interleave SRAM structure capable of achieving subthreshold working comprises a latch-type write driver circuit, a SARM memory unit array, a row decoding circuit, a column decoding circuit, sense amplifiers and a reading circuit. The latch-type write driver circuit is connected with the SARM memory unit array and the column decoding circuit. The SRAM memory unit array and the row decoding circuit are connected with the sense amplifiers and the reading circuit. The SRAM memory unit array is composed of a plurality of subthreshold SRAM basic memory units. An array-interleave arrangement mode is adopted by the SARM memory unit array. According to the array-interleave SRAM structure capable of achieving the subthreshold working, latch parts are added to the write driver circuit, so that the fact that when write operation is carried out, a 'half-selected' unit still has good stability even under the subthreshold working voltage is guaranteed, array interleave of the subthreshold SARM memory array is achieved, soft error rate of a SRAM is reduced, meanwhile, repeated use of the sense amplifiers is achieved, and area efficiency of the SRAM is improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a column interleaved static random access memory (Static Random Access Memory, SRAM) structure capable of realizing subthreshold operation. Background technique [0002] In order to realize the ultra-low power consumption of SRAM, the design of subthreshold SRAM has become a research hotspot in recent years. The 8-tube and 10-tube SRAM cell structures for single-ended reading have been proposed successively. These memory cells can realize the sub-threshold operation of SRAM and achieve the effect of low voltage and low power consumption; but the low voltage operation of these cells makes them in SRAM arrays It is difficult to achieve column interleaving, and all bits of a word can only be arranged adjacently, such as figure 1 As shown, a row of memory cells is composed of two logic words 10 and 11, and the three-bit memory cells constituting each logic word are arranged adja...

AI Technical Summary

Problems solved by technology

The structure is compatible with sub-threshold SRAM circuits, and solves the column interleaving problem of sub-threshold SRAM

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