Method, device and frequency meter for measuring pulse width

Abstract

The embodiment of the invention provides a method, a device, and a frequency meter which are used for measuring a pulse width. The method for measuring the pulse width includes: utilizing a to-be-measured signal which is delayed by a local standard clock to sample a front end error and a rear end error between an original signal to be measured and the to-be-measured signal which is delayed by a local standard clock; utilizing the local standard clock to record a high level time value of the original signal to be measured; and utilizing the sum of the time value and the front end error to subtract the rear end error to obtain the pulse width of the original signal to be measured. The method, the device, and the frequency meter which are used for measuring the pulse width enables the front end error and the rear end error to be directly obtained during the pulse width measuring process and utilize the carry chain resource inside the FPGA (Field Programmable Gate Array), so that the measuring error caused by wiring delay is avoided and the accurate measurement of the pulse width is achieved.

Description

technical field [0001] The invention relates to the field of signal measurement, in particular to a method, device and frequency meter for measuring pulse width. Background technique [0002] At present, it is often necessary to measure the pulse width of digital signals in the field of electronic applications. This kind of measurement usually adopts the pulse counting method, that is, a high-frequency clock pulse is used to count the high-level or low-level of the signal to be tested, and then the width of the signal to be tested is calculated according to the number of pulses, such as figure 1 shown. However, the signal to be tested is usually independent of the counting clock, and its rising and falling edges cannot fall exactly on the edge of the clock, so there will be errors in the pulse width measured by this method, such as figure 1 The front-end error Δf1 and the back-end error Δf2, the maximum measurement error of this measurement method is one clock cycle. For ...

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Problems solved by technology

[0008] 1. If you want to get better measurement results, you must use multiple phase-shift clocks and multiple counters, and these hard core resources in FPGA are very limited

[0009] 2. Due to the influence of the wiring delay in the FPGA itself, it is difficult to guarantee the accuracy of the relative delay of the clocks sent to each counter, that is, the phase relationship between the phase-shifted clocks cannot be guaranteed, which affects the final measurement results

[0010] 3. The signal to be tested enters the FPGA and undergoes necessary internal logic processing. Due to wiring delays, there will be some differences in the time it takes to reach different counters, which will also affect the final measurement results.

[0011] 4. The phase-shifted clock is obtained through the DCM in the FPGA, so there is a phase offset between different phase-shifted clocks

[0012] 5. Although the above method can improve the measurement accuracy by increasing the frequency of the counting clock, it can only reduce the measurement error value, but cannot avoid the error value

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