Distributed packet-switching chip model verification system and method

Abstract

The invention discloses distributed packet-switching chip model verification system and method and relates to the field of designing packet processing chips. The system comprises a core control module, a command line interface module, an SDK (software development kit) proxy interface module, a virtual network test meter module, a virtual chip configuration module and a C model package module. The core control module is a server program module. The command line interface module, the SDK proxy interface module, the virtual network test meter instrument, the virtual chip configuration module and the C model package module are client program modules. The system is a C / S / C (client / server / client) structured distributed system supporting three application scenarios, namely, system function model verification, software-hardware cooperated simulation verification and prototype verification. Modules required for different application scenarios are different. Verification closure time of the functions of the system at different levels can be shortened greatly, development efficiency is increased, and debugging cost is lowered.

Description

technical field [0001] The invention relates to the field of packet processing chip design, in particular to a distributed packet switching chip model verification system and verification method. Background technique [0002] With the deepening of the IP (Internet Protocol, Internet Protocol) process of global communication technology, the application requirements of packet switching chips are increasing, and the protocols related to packet switching are also increasing, which makes the development of such chips increasingly complex. [0003] In the actual chip development process, the common chip verification process is as follows: [0004] (1) System function model verification stage: the system uses high-level language (such as C language) to model the system function, that is, use the method of program modeling to simulate the packet processing function of the chip first, and then use it as a benchmark after the test is completed Carry out hardware description language ...

AI Technical Summary

Problems solved by technology

[0008] Due to the different methods used in the above four stages, it is generally necessary to design a separate set of hardware or software for each stage to implement separately, and the test cases cannot be reused, which makes the whole process extremely complicated

Each packet switching chip needs to support thousands of various network protocols. Therefore, a large number of tests at different levels are required to complete the verification. There will be a lot of iterations in the entire convergence process. Level of verification convergence time is lengthy, resulting in development progress lag

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