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DRAM (dynamic random access memory) double-chip stacking and packaging structure and packaging technology

A packaging structure, two-chip technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of large package thickness, poor electrical performance, poor reliability, etc., to reduce constraints, improve electrical performance, and save packaging costs. Effect

Active Publication Date: 2013-08-07
上海威固信息技术股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] In order to improve the problems of high cost, large package thickness, poor reliability and poor electrical performance in the traditional DRAM double-chip stack package, the purpose of the present invention is to provide a DRAM double-chip stack package structure using less bonding wires, and provide A kind of encapsulation process of this encapsulation structure

Method used

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  • DRAM (dynamic random access memory) double-chip stacking and packaging structure and packaging technology
  • DRAM (dynamic random access memory) double-chip stacking and packaging structure and packaging technology
  • DRAM (dynamic random access memory) double-chip stacking and packaging structure and packaging technology

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Embodiment Construction

[0043] Refer to the attached figure 1 , the figure includes some basic components, such as a substrate 16a provided with a substrate circuit, the substrate 16a is electrically connected to the outside, such as prefabricated solder balls 110a or pads, and the non-external connection side is packaged together with the packaged stacked chips, by The rectangular frame indicated by the molding compound designated by reference numeral 18a.

[0044] exist figure 1 In the shown structure, the components also include the first chip 12a, the second chip 11a, the intermediary substrate 13a, the silver glue 19a used to connect the first chip 12a and the substrate 16a, filled in the intermediary substrate 13a and the first chip 12a and The filler 111a between the second chips 11a (upper and last layer, in figure 1 Indicated with two wires), also includes gold wire 17a used as a bonding wire. Its composition and its construction are described in detail in the following.

[0045] exis...

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PUM

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Abstract

The invention discloses a DRAM (dynamic random access memory) double-chip stacking and packaging structure and packaging technology. According to the invention, an intermediary substrate is used for connecting a first chip and a second chip onto the substrate; restriction on a transmission line caused by the intermediary substrate is reduced; problems brought by the long-distance transmission of data are eliminated; and the packaging electrical properties are improved. The scheme is characterized in that only a bonding wire between the intermediary substrate and the substrate exists, thus being different from the characteristic of a gold wire slack above the second chip in the traditional DRAM package, the bonding wire slack is hedged by the second chip on the normal of the substrate, and the integral height of a packaging body is reduced. Due to the fact that the packaging body is only routed once, the gold wire use amount is reduced, and therefore the packaging cost is saved.

Description

technical field [0001] The invention relates to a DRAM double-chip stacking packaging structure and packaging technology. DRAM is an abbreviation of Dynamic Random Access Memory, that is, a dynamic random access memory. Background technique [0002] The explosive growth of information in modern society is inseparable from the rapid development and popularization of electronic products - especially consumer electronic products. Various electronic products have brought convenience to people's life, study and work. [0003] With the continuous development of science and technology and the improvement of consumers' requirements for electronic products, the functions of mobile phones and other consumer electronics continue to diversify, their performance and speed continue to increase, and the size is moving towards the trend of light, thin, short and small. To this end, integrated circuits use the following two methods to reduce the size and weight of products. The first is SOC ...

Claims

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Application Information

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IPC IPC(8): H01L25/065H01L23/492H01L21/60
CPCH01L2224/73253H01L2924/15311H01L2224/32145H01L2224/16225H01L2224/73265H01L2224/48227H01L2224/32225H01L2924/19107H01L24/73H01L2224/45144H01L2924/00012H01L2924/00
Inventor 户俊华刘昭麟栗振超孟新玲
Owner 上海威固信息技术股份有限公司
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