Quasi-Circular Matrix Serial Multiplier in dtmb Based on Shared Memory Mechanism

A quasi-circular matrix and shared storage technology, applied in the field of channel coding, can solve the problems of memory waste, large circuit power consumption, and waste, and achieve the effects of reducing memory requirements, simple structure, and reducing power consumption

Inactive Publication Date: 2016-03-16
RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented technology provides an improved method for processing data that uses both Layered Coding (LC) techniques like Quaternary Code Excited Linear Prediction coefficients (QCCs), which are used during encoding processes such as video compression or image recognition tasks. By utilizing this technique instead of traditional methods involving repetitive calculations, it saves money on hardware devices and reduces energy usage compared to previous technologies.

Problems solved by technology

Technologies described in this patents involve error correction systems such as Quadrature Ciruit Logic Code (QCC). These technical problem addressed include reducing energy usage during decoding operations while maintaining accuracy in data processing due to errors caused by nonlinearities between components.

Method used

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  • Quasi-Circular Matrix Serial Multiplier in dtmb Based on Shared Memory Mechanism
  • Quasi-Circular Matrix Serial Multiplier in dtmb Based on Shared Memory Mechanism
  • Quasi-Circular Matrix Serial Multiplier in dtmb Based on Shared Memory Mechanism

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Embodiment Construction

[0030] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

[0031] Since the generator polynomial f of the circulant matrix i,j Rotating right n bits is equivalent to rotating it left b-n bits, ie , then formula (8) can be rewritten as

[0032] m i F i , j = e i × b f i , j l ( b ) + e ...

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Abstract

The invention provides a quasi-cyclic matrix serial multiplier based on a shared storage mechanism in DTMB (Digital Terrestrial Multimedia Broadcasting), which is used for realizing multiplication of a vector m and a quasi-cyclic matrix F in standard multi-code-rate QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) approximate lower triangular coding of DTMB .The multiplier comprises a generator polynomial look-up table, a 3-bit delayer, three 127-bit buffers, three 127-bit binary multipliers, three 127-bit binary adders and three 127-bit shifting registers, wherein the generator polynomial look-up table is used for prestoring cyclic matrix generator polynomials in all code-rate matrices F, the 3-bit delayer is used for storing a data bit of the vector m in a sliding mode, the three 127-bit buffers are used for caching the generator polynomials, the three 127-bit binary multipliers are used for performing scalar multiplication on the data bit of the vector m and the generator polynomials, the three 127-bit binary adders are used for performing modulo-2 adding on a product and the contents of the shifting registers, and the three 127-bit shifting registers are used for storing the sum of one bit by cyclic shift to the left. The quasi-cyclic matrix serial multiplier provided by the invention is compatible with all code rates and has the advantages of less power consumption, simple structure, less consumption of a memory, low cost and the like.

Description

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Claims

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Application Information

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Owner RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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