Activation signal generating circuit and semiconductor memory device

Abstract

An activation signal generating circuit to which first and second activation signals which are pulse signals is applied and which generates an internal activation signal has a first delay element. The internal activation signal is activated based on the timing of the leading (activation transition) edges of the first and second activation signals. When the timing of the trailing (inactive transition) edge of the first active signal is earlier than the timing of the trailing edge of the second active signal, the internal active signal becomes inactive based on the timing of the trailing edge of the first active signal, and when the first When the timing of the trailing edge of the activation signal is later than the timing of the trailing edge of the second activation signal, the internal activation signal becomes inactive after a predetermined delay time based on the delay time of the first delay element.

Description

technical field [0001] Embodiments discussed herein are directed to an activation signal generating circuit and a semiconductor memory device. Background technique [0002] In capacitive cell type ferroelectric memory, non-volatile data is preserved by spontaneous polarization. By applying a voltage to the capacitive cell, a small charge is read when the polarization does not change, or a large charge is read when the polarization changes. This read is a data corrupt read, and thus the read data is rewritten in the capacitive cells immediately after being read. When ferroelectric memory is used in a system, the internal signal indicating when the power supply is turned on or when the power supply is turned off, or the reset signal of the on-board system is basically asynchronous, and therefore there is the question of how to Prevents data corruption while allowing these asynchronous signals to satisfy memory completion rewrite synchronous cycles. [0003] In addition, the...

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Problems solved by technology

When ferroelectric memory is used in a system, the internal signal indicating when the power supply is turned on or when the power supply is turned off, or the reset signal of the on-board system is basically asynchronous, and therefore there is the question of how to Prevents data corruption while allowing these asynchronous signals to satisfy memory completion rewrite synchronous cycles

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