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Phase-to-digital conversion circuit and phase-to-digital converter provided therewith

A technology of digital conversion and time difference, applied in the direction of time-to-digital converter, analog-to-digital converter, analog-to-digital conversion, etc., can solve the problems of unfavorable circuit scale and power consumption, and achieve reduced waiting time, high speed and power consumption, and low The effect of power consumption

Active Publication Date: 2013-08-21
PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, in the time-difference digital converter, 2 to the power of n latch circuits and comparators are required to generate an n-bit digital code, which is disadvantageous in terms of circuit scale and power consumption.

Method used

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  • Phase-to-digital conversion circuit and phase-to-digital converter provided therewith
  • Phase-to-digital conversion circuit and phase-to-digital converter provided therewith
  • Phase-to-digital conversion circuit and phase-to-digital converter provided therewith

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no. 1 approach

[0031] figure 1 The configuration of the time difference digital conversion circuit according to the first embodiment is shown. The time difference digital conversion circuit 10 according to this embodiment converts the time difference of the signals A and B into a 1-bit digital value D, adjusts the time difference of the signals A and B, and outputs signals A' and B'.

[0032] Specifically, the time-difference digital conversion circuit 10 includes a phase comparison unit 11 that compares the phases of the signals A and B to generate a digital value D, and outputs a signal whose phase is advanced among the signals A and B as a signal LEAD and a signal whose phase is delayed. Phase selection means 12 output as signal LAG and delay means 13 delay output signal LEAD. The output signal of the delay unit 13 corresponds to the signal A', and the signal LAG corresponds to the signal B'.

[0033] The delay unit 13 can be realized by a buffer circuit configured by cascading a plural...

no. 2 approach

[0042] Figure 8 The configuration of the time-to-digital converter according to the second embodiment is shown. The time difference digital converter 100 according to the present embodiment converts the time difference between the input signals S1 and S2 into an n-bit digital code, and the time difference digital converter 100 converts n-1 time differences according to the first embodiment into digital codes. The circuit 10 is cascaded, and the phase comparison unit 11 is connected at the last stage.

[0043] When the conversion input range of the time-difference digital converter 100 has been set to ±T, the delay time of the delay element 13 in each time-difference digital conversion circuit 10 is set to decrease sequentially from the first-stage time-difference digital conversion circuit 10. Half, that is, the delay time in the first stage is T, the delay time in the second stage is T / 2, and the delay time in the last stage (n-1th stage) is T / 2 n-2 . The digital output D...

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Abstract

A phase-to-digital conversion circuit that both converts the phase difference between two input signals to a one-bit digital value and adjusts the phase difference between said input signals to generate two output signals, is provided with: a phase-comparison means (11) that compares the phases of the two input signals and generates a digital value; a phase-selection means (12) that outputs a first signal and a second signal, the first signal being the input signal that is ahead in phase and the second signal being the input signal that is behind in phase; and a delay means (13) that delays the first signal and outputs the result. The phase-to-digital conversion circuit outputs two signals, namely the signal outputted by the delay means and the second signal.

Description

technical field [0001] The invention relates to a time-difference-to-digital converter for converting signal phase differences into digital values. Background technique [0002] In recent years, along with the development of digital phase synchronization circuits, researchers are actively developing time-to-digital converters that digitize analog information in the time direction. A typical time-to-digital converter works like this. The first signal is input into the inverter chain formed by connecting multiple inverter circuits in series, and the output of each inverter circuit is latched synchronously with the second signal, and the inverter circuit is detected. The state change point of the converter chain, thereby digitizing the phase difference or time difference of the first signal and the second signal. [0003] However, the time-to-digital converter requires 2 to the power of n latch circuits and comparators to generate an n-bit digital code, which is disadvantageou...

Claims

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Application Information

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IPC IPC(8): H03M1/12
CPCG04F10/005H03M1/50
Inventor 道正志郎高山雅夫三木拓司
Owner PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD