IO multiplexing port
A port and input port technology, applied in the direction of logic circuit coupling/interface, logic circuit connection/interface layout, etc. using field effect transistors, can solve the problems of inconvenient use, excessive device size, etc., and achieve convenient use, reduced volume, The effect of easy maintenance
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0014] Such as figure 1 As shown, an IO multiplexing port includes a first driver amplifier U1 and a second driver amplifier U2. The first driver amplifier U1 and the second driver amplifier U2 are connected in parallel between the port and the internal circuit. The input end of the amplifier U1 is connected to the port, the output end is connected to the internal circuit, the input end of the second drive amplifier U2 is connected to the internal circuit, and the output end is connected to the port. In this circuit, the relay J2 is the main switch that controls the LED light control circuit. After the relay J2 controls the LED light control circuit to be disconnected, when the first drive amplifier U1 is activated and the second amplifier U2 is turned off, the port is connected to the internal circuit. The port is the input port; when the first driving amplifier U2 is turned off and the second driving amplifier U2 is turned on, the internal circuit is connected to the port, and...
Embodiment 2
[0016] Such as figure 2 As shown, in this embodiment, on the basis of embodiment 1, the power supply circuits of the first driving amplifier U1 and the second driving amplifier U2 are respectively provided with a PMOS tube Q1 and a PMOS tube Q2, namely, the first driving amplifier U1 and the second driving amplifier U1. The negative pole of the power supply of the driving amplifier U2 is grounded, the positive pole of the power supply of the first driving amplifier U1 is connected to the power supply through the PMOS tube Q1, and the positive pole of the power supply of the second driving amplifier U2 is connected to the power supply through the PMOS tube Q2. The first driving amplifier U1 is controlled by the PMOS tube Q1, and the second driving amplifier U2 is controlled by the PMOS tube Q2, which facilitates the conversion of port input and output.
[0017] The gates of the above-mentioned PMOS transistor Q1 and PMOS transistor Q2 are connected to a controller, and the PMOS tr...
Embodiment 3
[0019] Such as image 3 As shown, in this embodiment on the basis of embodiment 2, an NMOS tube Q3 is provided between the power negative pole of the first drive amplifier U1 and the ground, and an NMOS tube Q3 is provided between the power negative pole of the second drive amplifier U2 and the ground. The gates of tube Q4, NMOS tube Q3 and NMOS tube Q4 are also connected to the controller, and a field effect tube is set at the ground, that is, the power supply of the first driving amplifier U1 can be controlled by PMOS tubes Q1 and NMOS Q3, PMOS tubes Q1 and NMOS Q3 When one is damaged, it does not affect the use of the entire device. At the same time, the power supply of the second drive amplifier U2 can be controlled by the PMOS transistors Q2 and NMOS Q4. When one of Q2 and Q4 is damaged, it does not affect the use of the entire device.
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 