Decoding circuit suitable for correcting miller code signal at high speed
A technology for decoding circuits and encoding signals, which is applied in the field of decoding circuits for high-speed correction of miller encoded signals, and can solve the problems of easy loss of decoding ability, limited pause period width, and complex circuits, etc.
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[0023] Specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.
[0024] Such as figure 1 As shown, the present invention discloses a decoding circuit suitable for high-rate correction miller encoded signals, the decoding circuit includes: a radio frequency receiver 1, an initiator 2, a first counter 3, a falling edge detector 4, a data decoder 5 and Clock generator 6 and data frame indicator 7.
[0025] The radio frequency receiver 1 receives a radio frequency signal with a pause period, and outputs a baseband signal and a synchronous clock signal. The radio frequency receiver 1 conforms to the ISO / IEC14443A type protocol, and is used to receive a radio frequency (RF) signal with a pause period of, for example, 13.56MHz and a bit rate of 847kbps, and convert the received RF signal into a first clock suitable for a digital circuit Signal rf_clk and data signal rf_din. The radio frequency signal with a pause...
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