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A nor-type flash memory

A memory and memory cell array technology, applied in static memory, read-only memory, information storage, etc., can solve the problem of large area occupied by peripheral drive circuits, and achieve the effect of reducing the number and area occupied

Active Publication Date: 2017-02-08
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of this, the purpose of the present application is to provide a NOR flash memory to solve the problem that the existing NOR flash memory peripheral drive circuit takes up too much area

Method used

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  • A nor-type flash memory

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Embodiment Construction

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

[0025] The embodiment of the present application discloses a NOR flash memory to solve the problem that the existing NOR flash memory occupies too much area.

[0026] refer to figure 1 , the NOR flash memory provided in Embodiment 1 of the present application is composed of a memory cell array and peripheral circuits.

[0027] Among them, the peripheral circuit includes 2P row decoding circuits 21 (ie X-decoder), 2P column decoding circuits 22 (ie YMUX) and P source line driver circuits 23...

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Abstract

The invention discloses an NOR flash memory. The NOR flash memory comprises a memory cell array and a peripheral circuit. The peripheral circuit comprises 2P row decoding circuits, 2P column decoding circuits and P source line driving circuits. The memory cell array comprises P double-array units. Each one of the P double-array units comprises 2 subarrays. P is positive integer. The subarrays are correspondingly connected to the row decoding circuits by word lines. The subarrays are correspondingly connected to the column decoding circuits by bit lines. The double-array units are in a one-to-one correspondence relationship with the source line driving circuits. The subarrays are connected to the source line driving circuits corresponding to the double-array units comprising the subarrays by source lines. The memory cell array is divided into an even number of the subarrays and each two of the subarrays use one source line driving circuit in common. Compared with the prior art, the NOR flash memory reduces the number of the source line driving circuits, reduces a memory occupation area and solves the existing technical problems.

Description

technical field [0001] The present application relates to the technical field of data storage, in particular to a NOR flash memory. Background technique [0002] NOR type (or non-logic type, also known as Linear technology) flash memory is a non-volatile semiconductor memory, mainly composed of a memory cell array and peripheral circuits. The peripheral circuit mainly includes a row decoding circuit (X-Decoder), a column decoding circuit (YMUX) and a source line driver circuit (SL-driver), wherein the row decoding circuit is used to drive the word line of the memory cell array, and the column decoding circuit Code circuits are used to drive the bit lines of the memory cell array. [0003] In order to improve the reading speed, the storage cell array of the existing NOR flash memory is usually divided into multiple independent sub-arrays (Cell Array), and the multiple sub-arrays are arranged in a row, and each sub-array has its own row decoding circuit, column decoding circ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/26G11C16/24
Inventor 龙爽陈岚陈巍巍杨诗洋陈丽
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI