Chip testing method and chip

A technology of chip testing and testing signals, which is applied in the direction of electronic circuit testing, measuring electronics, measuring devices, etc., can solve the problems of increased chip production costs, waste of resources, and inability to make full use of pin resources, so as to reduce testing costs and improve testing efficiency effect

Active Publication Date: 2013-10-30
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Embodiments of the present invention provide a chip testing method and a chip. By multiplexing the existing pins of the chip, the signals inside the chip are led out to the outside of the chip for observation and testing, whic

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0023] Example one

[0024] This embodiment provides a chip testing method, such as figure 1 As shown, the method includes:

[0025] 101. Multiplex the JTAG pins and function pins of the joint test behavior organization, and the multiplexed JTAG pins are used to configure the control signals of the custom registers in the test access port TAP, and the control signals are used to control The multiplexer MUX selects a specific test signal, and the multiplexed function pin is used to output the test signal.

[0026] Optionally, when step 101 is executed, it also includes:

[0027] 102. Add a custom register inside the TAP, where the custom register is used to generate a corresponding control signal according to the multiplexed configuration of the JTAG pin, and control the MUX to gate a specific test signal. It should be noted that there is no strict execution order for steps 101 and 102, and the two can be executed simultaneously or sequentially.

[0028] Optionally, after step 101 and ...

Example Embodiment

[0034] Example two

[0035] This embodiment provides a chip testing method, taking the interrupt signal and reset signal testing of the Watcgdog (watchdog) module as an example, such as image 3 As shown, the method includes:

[0036] 201. Determine an interrupt signal to be tested and a MUX that selects the interrupt signal.

[0037] Optionally, it can also be a reset signal. After the signal to be tested is determined, the custom register control signal corresponding to the test signal can be found according to the signal comparison table of the test signal and the control signal.

[0038] It should be noted that the interrupt signal and reset signal are mainly used to reset the system when the software runs away. The process is to send an interrupt notification first and then reset. In order to verify the integrity of the entire system reset mechanism, first confirm whether the Watcgdog module is issued correctly In addition to the interrupt signal and reset signal, the module does...

Example Embodiment

[0051] Example three

[0052] This embodiment provides a chip testing method. When the test signal output by the chip through the pin is abnormal, the abnormal position is located, for example, the output signal PWM OUT1 of the PWM (Pulse Width Modulation) module is verified. Lead the output signal PWMOUT1 of the PWM module to one of the MUX input ports, such as Figure 5 As shown, the method includes:

[0053] 301. Determine the PWM OUT1 signal to be tested and the MUX that selects the PWM OUT1 signal.

[0054] Optionally, after determining the signal to be tested, the custom register control signal corresponding to the test signal can be found according to the signal comparison table of the test signal and the control signal.

[0055] Wherein, before the determination of the PWM OUT1 signal to be tested, it further includes: multiplexing the JTAG pins and function pins, and the multiplexed JTAG pins are used to configure the custom register in the test access port TAP Control signa...

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Abstract

The invention discloses a chip testing method and a chip. The method includes the steps that a JTAG pin and a functional pin are reused, the JTAG pin which is reused is used for configuring a control signal of a self-defined register in a TAP, the control signal is used for controlling a specific testing signal gated by a MUX, the functional pin which is reused is used for outputting a testing signal, the self-defined register is added to the inner portion of the TAP, and the self-defined register is used for generating a corresponding control signal according to the configuration of the JTAG pin which is reused and controlling the specific testing signal gated by the MUX. The chip testing method is suitable for debugging an internal signal of the chip.

Description

technical field [0001] The invention relates to the technical field of integrated circuit signal interfaces, in particular to a chip testing method and a chip. Background technique [0002] JTAG (Joint Test Action Group, Joint Test Action Group) is an international standard test protocol, mainly used for internal testing of chips. The JTAG test allows multiple devices to be connected in series through the JTAG interface to form a JTAG chain, and to test each device in the JTAG chain separately. [0003] At present, the processor chip technology of handheld devices is getting higher and higher, and the internal complexity is also increasing, so the testing and positioning method of the chip is becoming more and more important. The traditional chip test is controlled by the JTAG interface. By defining a TAP (Test Access Port, test access port) inside the device, the internal nodes of the device are tested using a dedicated JTAG test tool, and the chip is determined according ...

Claims

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Application Information

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IPC IPC(8): G01R31/28G01R1/28
Inventor 刘宇李翔王锋何建波
Owner HUAWEI TECH CO LTD
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