Unlock instant, AI-driven research and patent intelligence for your innovation.

Layout of a MOS Array Edge with Density Gradient Smoothing

A density gradient, array technology, applied in the direction of comprehensive factory control, electrical components, circuits, etc., can solve problems such as increasing the cost of effective chip area

Active Publication Date: 2013-10-30
TAIWAN SEMICON MFG CO LTD
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Buffers enable better pattern uniformity of active MOS devices within the array, but increase the effective area overhead of the chip

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Layout of a MOS Array Edge with Density Gradient Smoothing
  • Layout of a MOS Array Edge with Density Gradient Smoothing
  • Layout of a MOS Array Edge with Density Gradient Smoothing

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0031] This document is described with reference to the drawings, wherein like reference numerals are generally used to refer to like elements herein, and the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth to facilitate understanding. It will be apparent, however, to one skilled in the art that one or more aspects described herein may be practiced with some of these specific details. In other instances, known structures and devices are shown in block form in order to facilitate understanding.

[0032] figure 1 Some embodiments of a semiconductor device array 100 with a buffer zone including a plurality of unit cells (C) 102 and a plurality of dummy cells (D) 104 are shown. Each unit cell 102 includes a metal oxide semiconductor (MOS) device. Each dummy cell 104 also includes the same metal oxide semiconductor (MOS) device as unit cell 102 , but dummy cell 104 is not el...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

Description

[0001] This application claims priority to US Provisional Patent Application Serial No. 61 / 640,073, entitled "Layout of a MOS Array Edge with Density Gradient Smoothing," filed April 30, 2012, the contents of which are incorporated herein by reference. technical field [0002] The present invention relates generally to the field of semiconductors, and more particularly to the layout of the edges of MOS arrays with smooth density gradients. Background technique [0003] Integrated circuits are typically formed in arrays in which the same metal-oxide-semiconductor (MOS) device geometry is repeated multiple times in a reticle region. The performance of integrated circuits depends on the pattern consistency between the shapes of the functional features within the MOS devices comprising the array to ensure that their electrical characteristics are matched. Because there is a density gradient between the edge of the array and the background circuitry, the pattern consistency of th...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/02H01L27/105
CPCH01L29/06H01L27/0207G06F17/5068G06F2119/18G06F30/39Y02P90/02
Inventor 彭永州周文升黄睿政
Owner TAIWAN SEMICON MFG CO LTD