Layout of a MOS Array Edge with Density Gradient Smoothing

A density gradient, array technology, applied in the direction of comprehensive factory control, electrical components, circuits, etc., can solve problems such as increasing the cost of effective chip area
CN103377883AActive Publication Date: 2013-10-30TAIWAN SEMICON MFG CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
TAIWAN SEMICON MFG CO LTD
Publication Date
2013-10-30

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Abstract

A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.
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Description

[0001] This application claims priority to US Provisional Patent Application Serial No. 61 / 640,073, entitled "Layout of a MOS Array Edge with Density Gradient Smoothing," filed April 30, 2012, the contents of which are incorporated herein by reference. technical field

[0002] The present invention relates generally to the field of semiconductors, and more particularly to the layout of the edges of MOS arrays with smooth density gradients. Background technique

[0003] Integrated circuits are typically formed in arrays in which the same metal-oxide-semiconductor (MOS) device geometry is repeated multiple times in a reticle region. The performance of integrated circuits depends on the pattern consistency between the shapes of the functional features within the MOS devices comprising the array to ensure that their electrical characteristics are matched. Because there is a density gradient between the edge of the array and the background circuitry, the pattern consistency of th...

Claims

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