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latch divider

A frequency divider and latch technology, applied in power oscillators, pulse technology, pulse generation, etc., can solve problems such as harmful effects on performance

Active Publication Date: 2016-04-13
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the frequency range of interest increases, these multilevel divider settings can introduce parasitic effects (i.e., parasitic inductance) that can deleteriously affect performance

Method used

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Examples

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Embodiment Construction

[0023] exist figure 1, reference numeral 100 generally refers to a latching frequency divider according to an example embodiment. The frequency divider 100 generally includes an LC resonator 102 , an input circuit 104 and a control circuit 108 . Resonator 102 typically includes inductors L1 and L2 coupled to output terminals (which provide output signals OUTP and OUTM) and receiving supply voltage VDD; alternatively, inductors L1 and L2 may be a single Inductor replacement. Each of resonator 102 and latch 104 includes a cross-coupled transistor pair Q1 / Q2 and Q11 / Q12, respectively (which may be NMOS transistors, for example). Input circuit 104 typically includes transistors Q5 and Q6 (which may be NMOS transistors, for example), each coupled to one of resonator 102 and latch 106 . The control circuit 110 generally includes two parts, which respectively include transistors Q7 and Q8 and transistors Q9 and Q10. Transistors Q5 , Q6 , Q8 and Q10 can also be NMOS transistors, f...

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Abstract

The present invention relates to a single-stage frequency divider suitable for operation at very high frequencies. Differential input signals (INP, INM) (eg, having a frequency of approximately 120 GHz) are divided by a frequency divider (100) to provide differential output signals (OUTP, OUTM) having a lower frequency (eg, approximately half). The divider provides an LC resonator (102) that uses the parasitic capacitance from the gates of the transistors (Q1, Q2) and the inductance of the inductors (L1, L2) to form an LC resonant circuit, thereby taking advantage of the normally degraded performance parasitic effects.

Description

technical field [0001] The present invention relates to frequency dividers, and more particularly to single-stage latching frequency dividers. Background technique [0002] There are many types of crossovers used in various frequency ranges. For many very high frequency ranges (ie greater than 30GHz), frequency dividers in CMOS were developed. However, many of these designs are multi-stage. As the frequency range of interest increases, these multilevel divider settings can introduce parasitic effects (ie, parasitic inductance) that can detrimentally affect performance. Thus, there is a need for more compact crossovers suitable for operation at very high frequencies (ie, 120GHz). [0003] Some examples of conventional circuits are PCT Publication No. WO / 2009 / 115865; U.S. Publication No. 2008 / 0303561; "A75GHz PLL Front-End Integration in 65nm SOICMOS Technology" by Kim et al. , pp.174-175; Lee et al., "A40-GHzFrequencyDividerin0.18-μmCMOSTechnology (40GHz frequency divider...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/00H03K21/00
CPCH03B19/14
Inventor R·古D·黄
Owner TEXAS INSTR INC