Method for forming semiconductor structure with metal gate electrode layer

Abstract

The invention provides a method for forming a semiconductor structure with metal gate electrode layers. The method includes the steps that a substrate is provided, and a first replacement gate electrode layer, a second replacement gate electrode layer, an etching barrier layer and an interlayer medium layer are formed on the surface of the substrate; the interlayer dielectric layer and the etching barrier layer are flattened until the first replacement gate electrode layer and the second replacement gate electrode layer are exposed; the first replacement gate electrode layer is removed to form a first opening, and the first opening is filled to form a first metal gate electrode layer; the first metal gate electrode layer, the interlayer dielectric layer, the etching barrier layer and the second replacement gate electrode layer are flattened, and a protective layer is formed on the surface of the first metal gate electrode layer; the second replacement gate electrode layer is removed to form a second opening, and the second opening is filled to form a second metal gate electrode layer; the second metal gate electrode layer, the interlayer dielectric layer, the etching barrier layer and the first metal gate electrode layer are flattened. According to the method for forming the semiconductor structure with the metal gate electrode layers, the performance of the semiconductor structure with the metal gate electrode layers can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a method for forming a semiconductor structure with a metal gate electrode layer. Background technique [0002] With the continuous shrinking of the feature size of the Complementary Metal-Oxide-Semiconductor (CMOS, Complementary Metal-Oxide-Semiconductor), the high-K metal gate electrode layer has widely replaced the traditional polysilicon gate electrode layer. The formation of the high-K metal gate electrode layer includes two types: a "gate-first" process and a "gate-last" process. Among them, the "gate-last" process is more widely used. The gate-last process in the formation process of the high-K metal gate electrode layer is specifically: [0003] Firstly, a substrate is provided, the surface of the substrate has a polysilicon dummy gate layer and sidewalls on both sides of the polysilicon dummy gate layer; [0004] Secondly, forming an etching barrier layer cover...

AI Technical Summary

Problems solved by technology

[0010] However, it has been found in practice that the performance of the semiconductor structure with a metal gate electrode layer formed by the above method is not good.

Images