Semiconductor package and preparation method thereof

Abstract

Provided is a semiconductor package which comprises a substrate, a semiconductor chip, a projection and a conductive member. The substrate comprises a grounding pattern and pads which are separated and electrically isolated; the semiconductor chip is mounted on the substrate, and includes an active surface and a non-active surface opposite to the active surface; the projection is arranged between the active surface and the pads and electrically connects the active surface with the pads; and the conductive member comprises at least one part which is arranged on the non-active surface and electrically connected with the grounding pattern.

Description

technical field [0001] The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package with improved electrical performance and a method of manufacturing the same. Background technique [0002] Common semiconductor packages include a semiconductor package in which a chip is front-mounted on a substrate and a semiconductor package in which a chip is flip-chip mounted on a substrate. In a semiconductor package in which the chip is mounted on the substrate, the back of the chip is mounted on the chip support part of the substrate through an adhesive layer, and the active surface of the chip is electrically connected to the pad on the surface of the substrate through the bonding wire, and the pad passes through the substrate. The internal leads are electrically connected to external connection terminals such as solder balls. In a semiconductor package in which a chip is flip-chip mounted on a sub...

AI Technical Summary

Problems solved by technology

[0003] As the complexity of circuit and package layouts increases, the width of circuit patterns becomes narrower and the spacing between circuit patterns becomes smaller, thus causing signal integrity issues

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