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System fault tolerance method for multiprocessor server

A multi-processor and system fault-tolerant technology, applied in the computer field, can solve problems such as component redundancy and waste of system configuration resources, and achieve the effects of ensuring reliability, easy promotion, and strong practicability

Inactive Publication Date: 2013-12-04
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Faced with products with such complex structures as multi-processor servers, some manufacturers adopt component redundancy methods, such as CPU redundancy and n CPUs as backup. Under normal conditions, only N-n CPUs are working, which is a huge waste. system configuration resource

Method used

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  • System fault tolerance method for multiprocessor server
  • System fault tolerance method for multiprocessor server
  • System fault tolerance method for multiprocessor server

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Embodiment Construction

[0020] The system fault tolerance method of a multi-processor server of the present invention will be described in detail below.

[0021] As attached figure 1 As shown, there is provided a system fault tolerance method for a multi-processor server. When the multi-processor server encounters an individual processor failure and reaches a certain level, the system actively degrades for fault tolerance. The system stops communicating with the faulty CPU, and safely unloads the faulty CPU from the system to avoid the development of a local problem into a global problem. This fault-tolerant design is at the cost of reducing configuration and improving system reliability. The specific process is:

[0022] Step 1. The system detects the processor failure and reports it to the monitoring management unit.

[0023] Step 2: The monitoring management unit analyzes and judges the fault, and sends an interrupt request to the system after reaching a certain fault level.

[0024] According to the CP...

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Abstract

The invention provides a system fault tolerance method for a multiprocessor server. The system fault tolerance method for the multiprocessor server has the following specific steps: a system detects a fault of the processor and reports the fault of the processor to a monitoring and managing unit; the monitoring and managing unit analyzes and judges the fault; after the fault achieves a certain fault level, an interrupt request is sent to the system; and after the system receives the interruption, configuration degradation is carried out according to a fault-tolerance strategy which is formulated in advance. The above steps aim at the multiprocessor server. Compared with the prior art, the system fault tolerance method for the multiprocessor server has the characteristic of improving the system reliability by lowering the configuration as the cost, and has the advantages of strong practicality and easiness in popularizing.

Description

[0001] Technical field [0002] The invention relates to the field of computer technology, in particular to a system fault tolerance method for a multi-processor server. Background technique [0003] With the rapid development of the server business, multi-processor servers have already become the mainstream in the market. At present, 4-way servers, 8-way servers, and even 16-way and 32-way servers extended by node controllers are also commonplace; but stand-alone interconnected processors The larger the number, the more problems may be caused. Taking a 4-way server as an example, assuming a single CPU failure rate is 0.01%, then the 4-way whole machine CPU failure rate is 0.04%; if the 8-way server uses the same quality CPU , The CPU failure rate of the whole machine is increased to 0.08%; it can be said that the more complex the system, the higher the probability of failure. [0004] Faced with such a complex product as a multi-processor server, some manufacturers adopt compo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/07G06F9/50
Inventor 李博乐林楷智
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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