Memory cascade and packaging methods, and device thereof

A memory cascading and memory technology, which is applied in the field of memory, can solve problems such as packaging and cascading troubles, and achieve the effect of avoiding costs, saving manpower, financial resources and time costs

Active Publication Date: 2013-12-04
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition to the cascaded memory, the required modules also need an additional address controller, which brings troubles to packaging and cascading

Method used

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  • Memory cascade and packaging methods, and device thereof
  • Memory cascade and packaging methods, and device thereof
  • Memory cascade and packaging methods, and device thereof

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Embodiment Construction

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0031] Such as Figure 1 to Figure 3 As shown, it is a block diagram of the memory cascading method of the present invention, a schematic diagram of memory addressing and a flow chart of the memory cascading method; in the present invention, each cascaded memory is called a sub-memory module, and the memory cascading of the present invention The method includes the following steps:

[0032] Step S1: Compatible the addressing control module and the decoding co...

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Abstract

The invention provides memory cascade and packaging methods, and a device thereof. The cascade method comprises the steps that: S1, an addressable control module and a decoding control module are compatible into a sub-memory; S2, an addressing control signal A [max+n:max+1] and a decoding control signal HLS [n-1:0] are configured, wherein max is a most significant bit of user input data, n is an integer, and 2n is the number of memories to be cascaded; S3, each bit of HLS [n-1:0] of each sub-memory is fixedly drawn to GND or VDD corresponding to n codes from all "0" to all "1", and a high n bit address mode is entered; S4, user inputted high n bit A [max+n:max+1] of address signal inputted by a user is compared with HLS [n-1:0], such that address signal AS [max:0] with selection information is obtained; and S5, the AS [max:0] signal is inputted into the addressing control module; address signal A [max:0] of a certain sub-memory is addressed by the addressing control module according to a final addressing produced by AS [max:0], such that addressing is completed. According to the invention, no additional controller is added, and small capacity can be enlarged to large capacity.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a memory cascading and packaging method and device thereof. Background technique [0002] Due to the limitation of the process, the capacity of the memory cannot be increased without limit. When the required memory capacity is greater than the maximum capacity of the developed product and the market demand is relatively small, it will take a lot of manpower, money and time to redevelop a product with a suitable capacity. It has great advantages for large-capacity storage. [0003] The current general method for expanding memory capacity is to add an extra controller outside the sub-memory to control the address and data selection of the cascaded memory. In addition to the cascaded memory, the required modules also need an additional address controller, which brings troubles to packaging and cascading. [0004] Therefore, how to propose a memory cascading and packaging method is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C5/04G06F13/16H01L25/065H01L21/98
CPCH01L2224/32145H01L2224/48145H01L2224/48147H01L2224/73265H01L2224/48247H01L2924/00012H01L2924/00
Inventor 刘会娟胡洪
Owner GIGADEVICE SEMICON (BEIJING) INC
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