Multi-layer memory system with three memory layers having different bit per cell storage capacities

Abstract

A multi-later memory and a method for operation are disclosed. The memory includes three or more layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer. The method may include the steps of directing host data directly into a first or second layer of the multi-layer memory upon receipt depending on a condition of the data. The method may also include copying data within a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer, as well as transferring data from one layer to the next higher bit per cell layer when layer transfer criteria are met.

Description

Background technique [0001] Non-volatile memory systems such as flash memory have been widely adopted in consumer products. Flash memory can be found in different forms, such as a portable memory card that can be moved between host devices or in the form of a solid-state drive (SSD) that is embedded in the host device. Two common memory cell architectures found in flash memory include NOR and NAND. In a typical NOR architecture, memory cells are connected between adjacent bit line source and drain diffusions extending in the column direction, and the control gates are connected to word lines extending along the rows of cells. A memory cell includes at least one storage element located over at least a portion of a channel region of the cell between a source and a drain. Thus, the level of programmed charge on the storage element controls the operating characteristics of the cell, which can then be read by applying an appropriate voltage to the addressed memory cell. [0002]...

AI Technical Summary

Problems solved by technology

There is an ongoing challenge in achieving the desired balance of performance, capacity and cost when designing flash devices using these types of flash memory cells

Images