Memory control equipment, semiconductor equipment and system board

Abstract

According to an embodiment, a memory control device controls a memory from / to which data are read / written by a processor. The memory control device includes a clock switcher and a control signal switcher. The clock receives as input a first clock and a second clock at a higher frequency than the first clock, supplies the first clock to the memory until the second clock becomes stable, and supplies the second clock after the second clock has become stable. The a control signal switcher starts supplying, to the memory, a first control signal for initializing the memory to a state allowing reading / writing of data by the processor while the first clock is being supplied to the memory, and supplies, to the memory, a second control signal according to the reading / writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized.

Description

[0001] Cross References to Related Applications [0002] This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-152108 filed on July 6, 2012; the entire contents of which are hereby incorporated by reference. technical field [0003] Embodiments described herein relate generally to memory control devices, semiconductor devices, and system boards. Background technique [0004] Portable information processing devices such as tablet devices and smartphones are expected to work efficiently using limited power. Therefore, reducing power consumption of information processing devices is a major issue. [0005] The power consumption of an information processing device can be reduced by stopping the high-frequency oscillator while the processor is waiting for input from the device in a standby state (a state in which the processor is continuously waiting for an interrupt), where the high-frequency oscillator is handled by the proc...

AI Technical Summary

Problems solved by technology

[0006] However, when the processor receives an interrupt and the information processing device resumes from the standby state, there is a problem that it takes time for the processor if the high-frequency oscillator is started for the first time and then the memory is initialized after the clock becomes stable Ready to read data from / write data to memory

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