Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification
A technology of chip design and low power consumption, which is applied in the field of low power consumption 8-tube SRAM chip design, can solve the problems of changing and destroying Node node signals, so as to improve stability, save sensitive amplifiers, and improve static noise tolerance Effect
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[0033] The SRAM of the present invention is composed of two different units, such as image 3 and 4 shown, where image 3 for N-type, Figure 4 It is P-type, the main difference is that the two tubes connected to the write bit line in the unit are of different types, N-type is NMOS, and P-type is PMOS. Both can store 1-bit digital signals, both can write 2-bit signals together, and can independently read 2-bit signals.
[0034] When writing operations, such as Figure 5 As shown, each column of N-type units is connected to P-type units through 4 switches. They are S0, S1, S2, and S3 respectively, and their switching conditions are determined by the input data. The specific truth table is shown in Table 1.
[0035] Table 1
[0036]
[0037] The following example illustrates the working process of the write operation, assuming that the 2-bit data to be written is "01". Before the write operation, the write bit lines connected to the N-type and P-type cells are prechar...
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