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Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification

A technology of chip design and low power consumption, which is applied in the field of low power consumption 8-tube SRAM chip design, can solve the problems of changing and destroying Node node signals, so as to improve stability, save sensitive amplifiers, and improve static noise tolerance Effect

Inactive Publication Date: 2014-01-29
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

In this new technology, there's some benefits compared to previous methods such as reducing energy usage by storing data into RAM instead of relying solely upon external components like an oscillator or crystal for timing purposes. Additionally, these improvements result in more stable operation over longer periods without losing any significant functionality. Overall, they make computing devices run faster while consuming less battery resources than before.

Problems solved by technology

Technological Problem: The technical problem addressed in this patented text relates to improving the efficiency and functionality of static random access memories (SSA) due to their ability to integrate faster operations within them without sacrificial storage areas or requiring extra components like clock circuits. Specifically, current SSAs require significant amounts of silicone RAM (SiO2) because they use expensive materials called stalls. To overcome these issues, new designs involving higher speeds and lower powers usage have been explored over recent years. Additionally, the challenge facing developers seeking fast response times and reduced energy consumptions per second continues to grow.

Method used

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  • Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification
  • Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification
  • Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification

Examples

Experimental program
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Effect test

Embodiment

[0033] The SRAM of the present invention is composed of two different units, such as image 3 and 4 shown, where image 3 for N-type, Figure 4 It is P-type, the main difference is that the two tubes connected to the write bit line in the unit are of different types, N-type is NMOS, and P-type is PMOS. Both can store 1-bit digital signals, both can write 2-bit signals together, and can independently read 2-bit signals.

[0034] When writing operations, such as Figure 5 As shown, each column of N-type units is connected to P-type units through 4 switches. They are S0, S1, S2, and S3 respectively, and their switching conditions are determined by the input data. The specific truth table is shown in Table 1.

[0035] Table 1

[0036]

[0037] The following example illustrates the working process of the write operation, assuming that the 2-bit data to be written is "01". Before the write operation, the write bit lines connected to the N-type and P-type cells are prechar...

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PUM

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Abstract

The invention relates to a design method of a low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification. The design method comprises the following steps: (1) connecting write bit lines of two different 8-pipe storage units (N-type and P-type) which are used in one SRAM through four switches; (2) in write operation, carrying out a bit line electric charge recycling technique on the write bit lines of the 8-pipe SRAM units, and completing the write operation by the two different 8-pipe storage units; and (3) in read operation, carrying out the same read operation on the two different 8-pipe storage units respectively with a read bit line classification structure, and completing the read operation by the read bit lines and sub bit lines thereof together. Compared with the prior art, the design method of the low-power-consumption 8-pipe SRAM chip based on electric charge recycle and bit line classification, which is provided by the invention, has the advantages of low energy consumption, high stability, good performance, simple structure and the like.

Description

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Claims

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Application Information

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Owner SHANGHAI JIAO TONG UNIV
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