How to make a floating gate transistor

Abstract

A floating-gate transistor manufacturing method includes the steps: providing a substrate; sequentially forming a gate oxide layer and a sacrificial layer on the substrate; performing graphical processing for the sacrificial layer and removing the sacrificial layer corresponding to a gate area; forming a nanometer silicon quantum dot grain array on the residual sacrificial layer and the gate oxide layer; removing the residual sacrificial layer and the nanometer silicon quantum dot grain array on the residual sacrificial layer; sequentially forming a dielectric layer and a control gate layer on the gate oxide layer and the residual nanometer silicon quantum dot grain array; sequentially performing graphical processing for the control gate layer, the dielectric layer and the gate oxide layer to form a gate structure. The floating-gate transistor manufacturing method is simple in process and easy to control.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a floating gate transistor. Background technique [0002] Compared with the traditional polysilicon floating gate structure, the floating gate structure and working mechanism of semiconductor silicon quantum dots allow the equivalent oxide thickness of the transistor to be greatly reduced, the integration degree is improved, and the power consumption is reduced. [0003] The methods of manufacturing floating gate transistors in the prior art include: [0004] refer to figure 1 As shown, a substrate 10 is provided, a gate oxide layer 20 of silicon dioxide material is formed on the substrate 10, a nano-silicon quantum dot grain array 30 (i.e. nanocrystal) is formed on the gate oxide layer 20, and the gate oxide layer A dielectric layer 40 made of silicon nitride covering the nano-silicon quantum dot grain array 30 is formed on the dielectric layer...

AI Technical Summary

Problems solved by technology

Because the materials of the dielectric layer 40 and the nano-silicon quantum dot grain array 30 are different, it is necessary to etch the nano-silicon quantum dot grain array 30 and the dielectric layer 40, and the etching is just stopped at the thinner gate dielectric. It is very difficult on layer 20, which ultimately makes the process more difficult to control and affects the performance of the device

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