Two-module redundancy configuration memory unit circuit used in programmable logic device

Abstract

A disclosed two-module redundancy configuration memory unit circuit used in a programmable logic device comprises a four-level interlocking memory unit consisting of four PMOS tubes and four NMOS tube, tow transmission tubes and two reset tubes. The two-module redundancy configuration memory unit circuit is capable of satisfying the configuration requirements of the programmable logic device by employing MOS tubes as less as possible, and improving the single event upset resistant threshold value of the programmable logic device.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, in particular to a dual-mode redundant configuration storage unit circuit for programmable logic devices. Background technique [0002] Since the 1970s, with the development of microelectronics technology, various types of general-purpose programmable logic devices (PLDs) have emerged. Among them, an FPGA configured with a storage unit SRAM based on device programming is widely used. Users can implement the required logic functions on SRAM through software, instead of having to design and manufacture ASIC chips by themselves. FPGA is a kind of high-density complex PLD. It consists of many independent programmable logic blocks, programmable interconnects, and programmable input / output blocks. Connections between logic blocks and with I / O blocks are made through programmable interconnect switches. Programmable resources can be controlled by downloading the configuration code stream ...

AI Technical Summary

Problems solved by technology

However, in some applications, the configuration memory unit SRAM bit state in the FPGA is prone to be flipped by single event radiation

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