Low-resource-consumption DICE trigger design method based on commercial technology

A technology of resource consumption and design method, applied in pulse generation, electrical components, generation of electrical pulses, etc., can solve the problems of large layout design area and high overhead, and achieve the effect of improving reliability and strong pertinence

Pending Publication Date: 2021-10-22
XIAN INSTITUE OF SPACE RADIO TECH
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0004] The technical problem solved by the present invention is: Aiming at the current prior art, in ASIC design, the layout design area of ​​the traditional DICE flip-flop is relatively large and the cost is high, a low resource consumption DICE trigger based on commercial technology is proposed device design method

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  • Low-resource-consumption DICE trigger design method based on commercial technology
  • Low-resource-consumption DICE trigger design method based on commercial technology
  • Low-resource-consumption DICE trigger design method based on commercial technology

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Embodiment Construction

[0026] In order to improve the SEU protection capability of ASICs developed using 65nm anti-adding libraries, and minimize the area and performance overhead, a low-resource-consumption DICE flip-flop design method based on commercial processes is proposed, without affecting the chip design process. Under such circumstances, starting from the SEU occurrence mechanism of 65nm commercial MOS devices, using the node flip and recovery effect generated by multi-node charge sharing collection, the anti-SEU reinforcement design is realized at the physical layout level of the DICE flip-flop unit, achieving low cost, The purpose of low resource consumption and high reliability.

[0027] The specific flow of the DICE flip-flop design method is as follows:

[0028] (1) Adjust the physical position of the MOS tube of the cross-coupled inverter to reduce the recovery threshold of the latch of the flip-flop;

[0029] Among them, the specific method of adjusting the MOS transistor of the cro...

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Abstract

A low-resource-consumption DICE trigger design method based on a commercial technology starts from a 65nm commercial MOS device SEU generation mechanism under the condition that a chip design process is not affected, node overturning generated by multi-node charge sharing collection is utilized to recover a Recovery effect, anti-SEU reinforcement design is achieved on a physical layout level of a DICE trigger unit, the purposes of low cost, low resource consumption and high reliability are achieved.

Description

technical field [0001] The invention relates to a low-resource consumption DICE flip-flop design method based on a commercial technology, and belongs to the field of CMOS integrated circuit space single event effect protection. Background technique [0002] CMOS integrated circuits are susceptible to single-event upsets and single-event transients in space radiation environments. The generation of SET / SEU is when high-energy ions are incident on the drain region of the off-state MOS transistor, and electron-hole pairs will be generated on its path. Under the action of an electric field, for NMOS, electrons drift to the drain, and for PMOS, holes drift to the drain, thereby generating a transient pulse SET. If there is a reverse positive feedback circuit in the area generated by the SET, and the pulse of SET After the energy is collected by the positive feedback loop and changes the logic state of the feedback loop, SEU will be generated. [0003] The DICE latch is a common...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/013
CPCH03K3/013
Inventor 张建赖晓玲王倩琼巨艇邓星星戴璐
Owner XIAN INSTITUE OF SPACE RADIO TECH
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