Package structure

A technology of packaging structure and plastic sealing layer, which is applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of low packaging efficiency and achieve the effects of improving efficiency, reducing area and increasing distance

Active Publication Date: 2017-09-08
NANTONG FUJITSU MICROELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Existing lead frame packages can only be packaged for a single semiconductor chip and lead frame, and the packaging efficiency is low

Method used

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Embodiment Construction

[0023] When encapsulating an existing lead frame, please refer to figure 1 , firstly, the wafer needs to be cut to form the semiconductor chips 14 one by one, and then the metal wires 17 are formed through the wire bonding process. The plastic encapsulation material 18 encapsulates the semiconductor chip 14 and the lead 16, and the existing encapsulation process can only implement the encapsulation of a single semiconductor chip and the lead, and the encapsulation efficiency is low. In addition, the pins 16 are arranged around the semiconductor chip 14, and the pads 15 on the semiconductor chip 14 need to be electrically connected to the surrounding pins 16 through metal wires 17, so that the entire package structure occupies a larger volume , which is not conducive to the improvement of the integration degree of the packaging structure.

[0024] To this end, the present invention provides a package structure including a pre-sealed panel, and the pre-sealed panel and the pins...

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Abstract

A packaging structure comprises a lead frame, first plastic-sealing layers filled into openings between adjacent pins, first metal protruding blocks arranged on the first surfaces of the pins, and a pre-packaging face plate. The lead frame comprises a first surface and a second surface, the lead frame is provided with a plurality of bearing units and middle ribs used for fixing the bearing units, each bearing unit comprises a plurality of independent pins, and the openings are formed between the adjacent pins. The pre-packaging face plate comprises a second plastic-packaging layer, wherein a plurality of integration units distributed in a matrix mode are arranged in the second plastic-packaging layer, at least one semiconductor chip is arranged in each integration unit, a plurality of welding discs are arranged on the surface of the semiconductor chip, the second plastic-packaging layer is exposed of the welding discs on the semiconductor chip, the welding discs are provided with second metal protruding blocks which are provided with welding flux layers, the pre-packaging face plate is inversely arranged on the first surface of the lead frame, and the second metal protruding blocks are connected with the first metal protruding blocks on the pins in a welding mode. The integration level of the packaging structure is improved.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a packaging structure. Background technique [0002] With the development of electronic products such as mobile phones, notebook computers, etc. towards miniaturization, portable, ultra-thin, multimedia and low-cost to meet the needs of the public, high-density, high-performance, high-reliability and low-cost packaging forms and their Assembly technology has developed rapidly. Compared with the expensive BGA (Ball Grid Array) and other packaging forms, the rapidly developing new packaging technology in recent years, such as the Quad Flat No-lead Package (Quad Flat No-lead Package), has good thermal performance and electrical characteristics. The many advantages of performance, small size, low cost and high productivity have triggered a new revolution in the field of microelectronic packaging technology. [0003] figure 1 It is a schematic structural diagram of an existin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/495
CPCH01L24/97H01L2224/16245H01L2224/48091H01L2224/48247H01L2924/15788H01L2924/18165H01L2924/00014H01L2924/00
Inventor 陶玉娟刘培生
Owner NANTONG FUJITSU MICROELECTRONICS
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