Laminated packaging method for semiconductor

Abstract

The invention provides a laminated packaging method for a semiconductor. The method includes the steps of manufacturing an upper packaging body, manufacturing a lower packaging body with a chip in a packaged mode, and packaging the upper packaging body and the lower packaging body in a laminated mode. The step of manufacturing the lower packaging body with the chip in the packaged mode includes the substep 101 of providing a substrate for manufacturing the lower packaging body, the substep 102 of forming metal convex points on the upper surface of the substrate, the substep 103 of connecting the chip to the upper surface of the substrate in an inverted installation mode, the substep 104 of fixing and packaging the chip to the substrate by means of plastic package bottom padding to form a plastic package body with which the metal convex points are coated, the substep 105 of polishing the plastic package body and exposing the metal convex points and the substep 106 of cleaning the metal convex points and forming solder balls or a weldable film layer on the lower surface of the substrate. According to the packaging method, the bottom of the chip is filled with the plastic package bottom padding in packaging of the chip of the lower packaging body, and meanwhile the chip is packaged and fixed to the substrate. Accordingly, restrictions on sizes of the solder balls which are interconnected in the existing packaging technology are removed, the problem that the packaging bodies warp is reduced, the plastic package body is polished, so that the thickness of the whole plastic package body is decreased, the height of the metal convex points is decreased, and packaging density is high.

Description

technical field [0001] The invention relates to a semiconductor packaging method, in particular to a semiconductor stack packaging method. Background technique [0002] The emergence of POP (Package on Package) technology blurs the boundary between the first-level packaging and the second-level assembly. While greatly improving the logic operation function and storage space, it also provides end users with the possibility to freely choose the combination of devices. , production costs can be more effectively controlled. [0003] In the POP structure, the memory chip is usually connected to the substrate by bonding, while the application processor chip is connected to the substrate by flip-chip. The memory chip package is directly stacked on the application processor package, and they are usually soldered with solder balls. connect. In this way, the upper and lower structures reduce the interconnection distance between the two chips to save space and obtain better signal in...

AI Technical Summary

Problems solved by technology

As the connection between memory chips and logic chips tends to be higher density, the POP structure of traditional packaging is already very limited. During the traditional packaging process, problems such as package warpage are often encountered

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