Semiconductor device and method for preparing same

Abstract

The present invention relates to a semiconductor device and a method for preparing the same. The method comprises the steps of providing a semiconductor substrate on which a plurality of laminations are formed, wherein the laminations comprise a grid material layer, a grid dielectric layer, a channel layer and another one grid dielectric layer which are deposited orderly; patterning the relative two surfaces in the laminations to form a stepped grid lamination of which the area is reduced orderly from bottom to top and expose a part of the grid material layer to thereby form a grid structure, patterning the laminations at the two sides of the grid structure to form a stepped source-drain lamination of which the area is reduced orderly from bottom to top and expose a part of the channel layer to thereby form a source-drain area, and depositing a first dielectric layer on the substrate; forming a first interlayer dielectric layer on the first dielectric layer; and finally forming a grid electrode and a source-drain electrode to thereby form a 3D transistor. With the arrangement of a 3D structure, a drain current and the integration level of the semiconductor device are increased, and further the performance of the device is improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular, the invention relates to a semiconductor device and a preparation method thereof. Background technique [0002] The improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has progressed to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, especially when semiconductor device dimensions drop to 22nm or below, challenges from manufacturing and design have led to three-dimensional design Such as the development of Fin Field Effect Transistor (FinFET). [0003] Compared with the existing planar transistors, the FinFET device has more superior performance in terms of channel control and reducing shallow channel effects; the planar gate structure is arranged above the channel, and the gate in the FinFET The...

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Problems solved by technology

[0006] Therefore, although there are junction-less transistors in the prior art, the drain current of the current fabrication method and obtained transistors is relatively small, and at the same time, the degree of integration is also affected as the size decreases, making semiconductor devices The performance is limited, so the current preparation method needs to be improved to eliminate the above problems

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