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Circuit structure for eliminating short circuit currents

A technology for circuit structure and short-circuit elimination, which is applied in the direction of reliability improvement and modification, can solve the problems of inconvenience, increase of power consumption and cost, increase of circuit power consumption and cost, etc., and achieve reduction of power consumption and calorific value, cost and power consumption Low, avoiding the effect of increasing power consumption and cost

Active Publication Date: 2014-05-14
中山芯达电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this method can eliminate the short-circuit current I s , but it needs to add multiple logic circuit elements, which will undoubtedly increase the power consumption and cost of the circuit
Moreover, when multi-level complementary circuits are cascaded, it is very inconvenient to add corresponding circuit elements before each level of circuit, and the increase in power consumption and cost will be more obvious in large-scale integrated circuit applications.

Method used

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  • Circuit structure for eliminating short circuit currents
  • Circuit structure for eliminating short circuit currents
  • Circuit structure for eliminating short circuit currents

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0049] The first-level drive circuit 1 includes a PMOS-type third transistor 11 and an NMOS-type fourth transistor 12. The source of the third transistor 11 is connected to the power supply VDD, and the drain is connected to the first-level drive circuit. The first output terminal 103 of 1; the source of the fourth transistor 12 is connected to the signal ground GND, and the drain is connected to the second output terminal 104 of the first-level driving circuit 1; the gate of the third transistor 11 and the gate of the fourth transistor 12 are commonly connected to the first input terminal 101 of the first-level driving circuit 1 .

[0050] The second-level drive circuit 2 includes a PMOS-type fifth transistor 21 and an NMOS-type sixth transistor 22. The source of the fifth transistor 21 is connected to the power supply VDD, and the gate is connected to the second-level drive circuit. 2's first input end (i.e. the first output end 103 of the first-level drive circuit 1); the s...

no. 2 example

[0059] A schematic diagram of a logic "AND" circuit adopting the circuit structure of the present invention, which includes a first-stage drive circuit composed of transistors 81, 82, 83 and 84, a second-stage drive circuit composed of transistors 91 and 92, and a second-stage drive circuit composed of transistors 61 and 62. The first time delay unit composed of, and the second time delay unit composed of transistors 71 and 72;

[0060] The first stage drive circuit is provided with a first input terminal 101, a second input terminal 102, a first output terminal 103 and a second output terminal 104; the first time delay unit and the second time delay unit are located at the first Between the first output terminal 103 and the second output terminal 104 of the stage driving circuit.

[0061] The first delay unit includes a PMOS type first transistor 61 and an NMOS type second transistor 62 .

[0062] The source of the first transistor 61 is connected to the first output termina...

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Abstract

The invention provides a circuit structure for eliminating short circuit currents. The circuit structure for eliminating the short circuit currents is characterized in that the circuit structure for eliminating the short circuit currents at least comprises a first level driving circuit and a first time delay unit, wherein the first level driving circuit is at least provided with a first input end, a first output end and a second output end, and the first time delay unit is arranged between the first output end and the second output end and comprises a first transistor and a second transistor. The moments of switching on and switching off of switches in a complementary type circuit are staggered through a short time delay, short circuit currents Is causing instability of the circuit are eliminated fundamentally, and safety and stability of the whole circuit are protected. Meanwhile, due to the fact that the electrical signal output of the first output end and the electrical signal output of the second output are asynchronous, the moments of switching on and switching off of the switches in the follow-up cascaded complementary type circuit are staggered, and the effect of eliminating the short circuit currents causing instability of the circuit is performed. The circuit structure for eliminating the short circuit currents has the advantages of being safe, stable, free of short circuit loss, low in cost and the like, and is suitable for innovative improvement of a standard cell library.

Description

technical field [0001] The invention relates to a standard unit circuit, in particular to a circuit structure for eliminating short-circuit current. Background technique [0002] In complementary driving circuits, especially the structure commonly used in standard unit circuits, it is generally composed of two MOS transistors (refer to the attached figure 1 , including a first-stage circuit composed of transistors 11 and 12, and a second-stage circuit composed of transistors 21 and 22), to realize outputting high or low level signals to subsequent circuits. However, whenever the level of the input terminal of the complementary drive circuit is switched between high and low values, since the MOS transistor switches perform opening and closing actions under the synchronous clock, two MOS transistor switches are turned on at the same time at a certain moment. situation (see attached image 3 , when the input voltage V IN At the rising time t2 to t4 or the falling time t7 to ...

Claims

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Application Information

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IPC IPC(8): H03K19/003
Inventor 方镜清
Owner 中山芯达电子科技有限公司