Synchronizing circuit and clock data recovery circuit including the same

Abstract

A synchronizing circuit that is capable of generating a reproduced clock signal synchronized with a reference clock signal without causing a false lock and a clock data recovery circuit including the same are provided. To generate a clock signal synchronized with a reference clock signal associated with a data transition point that appears every predetermined period in an input data signal, the following false-lock avoidance processing is performed. That is, precharging of a first line is started when a phase control voltage applied to the first line by a charge pump falls below a lower-limit reference voltage, and the precharging of the first line is continued until the phase control voltage exceeds an upper-limit reference voltage.

Description

technical field [0001] The present invention relates to a synchronization circuit that generates a reproduced clock signal synchronized with a reference clock signal, and a clock data recovery circuit (hereinafter referred to as a CDR circuit) including the synchronization circuit. Background technique [0002] Currently, as a high-speed serial data communication method, an embedded clock method in which a clock signal is superimposed on a data signal and transmitted is used. [0003] A CDR circuit is installed in a receiving device of a communication system employing an embedded clock method, and the CDR circuit acquires a regenerative clock from the received data signal that is phase-synchronized with the transition point of the data by utilizing the periodicity of data transition in the received data signal signal (for example, refer to Patent Document 1's Figure 5 ). This CDR circuit includes a PLL (phase locked loop: phase locked loop) circuit composed of a phase / freq...

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Problems solved by technology

[0006] However, if the phase / frequency detector in the PLL circuit malfunctions due to external noise, for example, only a signal corresponding to the phase advance (or delay) is continuously supplied to the charge pump, the output of the charge pump is fixed to zero level

Therefore, later, when a new data signal is received, the PLL circuit starts initial synchronization from the state where the output of the charge pump is at zero level, so at this time, the synchronization circuit with a feedback loop such as the PLL circuit may be synchronized with the desired Frequency different frequency while false lock

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