Variation-tolerant periodic synchronizer

Abstract

A method and a system are provided for variation-tolerant synchronization. A phase value representing a phase of a second clock signal relative to a first clock signal and a period value representing a relative period between the second clock signal and the first clock signal are received. An extrapolated phase value of the second clock signal relative to the first clock signal corresponding to a next transition of the first clock signal is computed based on the phase value and the period value.

Description

technical field [0001] The present invention relates to circuits, and more particularly, to synchronous circuits. Background technique [0002] Many digital systems have multiple clock domains. Therefore, when a signal moves from one clock domain to another, it must be synchronized to avoid metastability and synchronization failures. If two clocks have fixed frequencies, then the phase relationship between the two clocks is periodic, at the beat frequency of the two clocks. By exploiting this periodic phase relationship, a periodic synchronizer can be simpler, have lower latency, and have lower failures than a synchronizer that has to deal with clock domains across at least one of the clocks operating at a variable frequency probability. [0003] The design of synchronizers is more complicated when at least one of the clocks operates at a variable frequency. Typically, an asynchronous first-in-first-out (FIFO) is used to synchronize signals passed between clock domains w...

AI Technical Summary

Problems solved by technology

FIFOs also add several cycles of latency because the Gray-coded input and output pointers of the FIFO must be synchronized through multiple flip-flops to reliably route signals across clock domains

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