Manufacturing method of dummy gate in gate-last technology and dummy gate in gate-last technology

Abstract

The invention provides a manufacturing method of a dummy gate in the gate-last technology. The method includes the steps that a semiconductor substrate is provided; a gate electrode oxide layer is grown on the semiconductor substrate; bottom layer amorphous silicon is deposited on the gate electrode oxide layer; a hard mask of an ONO structure is deposited on the bottom layer amorphous silicon; top layer amorphous silicon is deposited on the hard mask of the ONO structure; a hard mask layer is deposited on the top layer amorphous silicon; photoresist lines with the width between 32 nm and 45 nm are formed on the hard mask layer; with the photoresist lines as the standard, the hard mask layer, the top layer amorphous silicon, the hard mask of the ONO structure and the bottom layer amorphous silicon are etched, and the photoresist lines, the hard mask layer and the top layer amorphous silicon are removed. The invention further provides the dummy gate in the gate-last technology. Through the technical scheme, the key sizes and the profile morphology of a gate electrode can be accurately controlled, the roughness of gate electrode lines can be effectively improved, and performance and stability of a device are guaranteed.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a gate-last process dummy gate and a gate-last process dummy gate. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is getting smaller and smaller. In order to reduce the parasitic capacitance of the gate of MOS transistors and improve the device speed, the gate stack of high K gate dielectric layer and metal gate structure is introduced into MOS transistors. In order to avoid the influence of the metal material of the metal gate on other structures of the transistor, the gate stack structure of the metal gate and the high-K gate dielectric layer is usually fabricated by a “gate last” process. [0003] The so-called gate-last process refers to providing a semiconductor substrate on which a dummy gate structure and an etch barrier layer covering the d...

AI Technical Summary

Problems solved by technology

But at present, due to the limitations of physical mechanism, process technology and processing methods, in the 45nm~32nm technology band, the critical size of the dummy gate and the cross-sectional shape of the dummy gate cannot be precisely controlled, which affects the accuracy of the gate lines. roughness, the performance and stability of the device cannot be guaranteed

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