A high-speed flash and alternating comparison successive approximation analog-to-digital converter

Abstract

The invention discloses a high speed quick flashing plus alternating comparison type successive approximation analog to digital converter which comprises a first sampling circuit, a second sampling circuit, a first capacitance array, a second capacitance array, a 4 bit quick flashing type sub-ADC, an alternate comparator, a logic control circuit and a digital weighted circuit, wherein both the first capacitance array and the second capacitance array comprise a thermometer code high effective bit capacitance array and a sub-binary low effective bit capacitance array. By the adoption of the high speed quick flashing plus alternating comparison type successive approximation analog to digital converter, through adding the quick flashing type sub-ADC before a cycle parsing process, cycle times can be effectively reduced and parsing time is shortened; through the introduction of the alternate comparator, the comparator reset time in a traditional structure is eliminated, the speed bottleneck is broken through and parsing speed is accelerated; the added quick flashing type sub-ADC bit number is low, and interpolation technology and a dynamic circuit structure are adopted, so that the increased power consumption is small, and the achieving cost is low cost is achieved; moreover, the introduced alternate comparator does not increase the total comparison times, so that power consumption does not increase.

Description

technical field [0001] The invention relates to the field of successive approximation analog-to-digital converters, in particular to a high-speed flash plus alternating comparison successive approximation analog-to-digital converter. Background technique [0002] The wireless communication industry and large-scale digital integrated circuit technology have developed rapidly in the past ten years, and the analog-to-digital converter (ADC), as a bridge between the analog world and the digital world, has also made a great leap forward, especially the successive approximation With the continuous advancement of the deep submicron process, the speed of SARADC has increased by dozens of times. Compared with ADCs of other structures, SARADC is a structure with medium and high precision, medium and high speed, low power consumption and small footprint. However, the traditional SAR ADC still cannot replace the position of the pipelined analog-to-digital converter (PIPELINE ADC) in hi...

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Problems solved by technology

[0006] Taking the common 10bit SARADC as an example, on a typical 130nm CMOS process node, the T determined by the above delay ADC It is difficult to be less than 12.5ns, that is, the sampling frequency is limited below 80MSPs

[0007] In higher-speed applications, higher-speed PIPELINE ADCs are usually used to meet system requirements, however, PIPELINE ADCs consume significantly more power due to their internal necessary high-performance op amps, which can be significant in many portable and battery-powered applications To shorten the battery life, how to effectively increase the sampling frequency while maintaining the advantage of low power consumption of SAR ADC has become an urgent problem to be solved by those skilled in the art

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