Testing structure and method for field-effect transistor overlap capacitance

Abstract

The invention provides a testing structure and method for field-effect transistor overlap capacitance. The testing method comprises the steps that firstly, a field-effect transistor is firstly provided as a tested structure, and an overlap region exists in the grid structure of the field-effect transistor, a drain region and a source region in the vertical direction; the total capacitance C1 between the grid electrode and the drain electrode of the field-effect transistor is obtained through testing; then a testing structure is designed, and at least comprises a substrate, a shallow trench isolation region arranged in the substrate, a grid structure covering the shallow trench isolation region, a drain region, a source region, a first connecting wire arranged on the drain region and a second connecting wire arranged on the source region, and the drain region and the source region are arranged in the substrate and on the two sides of the shallow trench isolation region respectively; the total capacitance C2 between the grid electrode and the drain electrode of the testing structure is obtained through testing; the C1 is reduced by C2 to obtain the overlap capacitance of the tested structure. The testing method for the overlap capacitance is easy to operate, and the overlap capacitance of the field-effect transistor can be obtained conveniently.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a test structure and method for overlapping capacitance of field effect transistors. Background technique [0002] In the semiconductor industry, there is a continuous increase in the operating speed of integrated circuits. This growing demand drives the continuous upgrading of electronic devices, and the increase in the speed of electronic devices has led to a continuous reduction in the size of the device. For high-frequency applications of metal-oxide-semiconductor field-effect transistors (MOSFETs), the influence of parasitic capacitance (Parasitic Capacitance) inside the metal-oxide-semiconductor field-effect transistor must be taken into account. The parasitic capacitance inside the metal oxide semiconductor field effect transistor includes the overlap capacitance (Overlap Capacitance) of the gate and the drain. For example, ring oscillators have extremely high osci...

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Problems solved by technology

However, in the silicide back-end process (silicide last process), silicide (silicide) will only be formed where the connection line is opened. For the performance of the device, the connection line is generally made into a rectangle, such as Figure 4 As shown, this structure can no longer use the above method to obtain the required overlapping capacitance

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