Memory electric leakage controlling apparatus

Abstract

The invention discloses a memory electric leakage controlling apparatus. An electric leakage control unit adjusts at least one of the grid voltage and the basic voltage, applied by a memory circuit in a standby state, of a first power transistor and a second power transistor, so that inhibition on the leakage current flowing through the first power transistor and the second power transistor is enhanced.

Description

technical field [0001] The present invention relates to a leakage control device, and in particular to a leakage control device of a memory. Background technique [0002] Dynamic random access memory (dynamic random access memory, DRAM) is a very common semiconductor storage device at present. The sense amplifier of the conventional DRAM usually uses a P-type power transistor and an N-type power transistor as power switches to provide the sense amplifier power when the sense amplifier is turned on. [0003] However, in the standby mode of the traditional DRAM, the storage elements are pre-charged, and the bit line and the complementary bit line are pre-charged to a predetermined voltage. flat. For example, the bit line and the complementary bit line are precharged to supply voltage VDD, half supply voltage VDD / 2, ground voltage VSS or other reference voltages. In this way, the channels of the P-type power transistor and the N-type power transistor used as the power switch...

AI Technical Summary

Problems solved by technology

In this way, the channels of the P-type power transistor and N-type power transistor used as the power switch of the sense amplifier cannot be completely closed, and a leakage current will be generated on the P-type power transistor and the N-type power transistor, resulting in additional power consumption

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