Full-duplex and half-duplex converter and conversion method
A half-duplex and full-duplex technology, which is applied in the direction of duplex signal operation, can solve the problems of data loss and bit error rate, and achieve the effect of ensuring accuracy and solving communication compatibility problems
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Example Embodiment
[0043] Specific implementation mode 1: Combination figure 1 To illustrate this embodiment, the full-duplex and half-duplex converters described in this embodiment include a half-duplex signal acquisition module 1, a full-duplex data processing module 2, and a tri-state gate integrated circuit 3. The data processing module 2 includes a physical layer receiving terminal 2-1, a physical layer transmitting terminal 2-2 and an FPGA chip 2-3;
[0044] The half-duplex signal acquisition module 1 is implemented using an RS485 chip, and the physical layer receiving end 2-1 and the physical layer transmitting end 2-2 are both implemented using a 422 serial port driver module;
[0045] The 422R+ port and 422R- port of the physical layer receiving end 2-1 are respectively connected to the data signal output + port and data signal output port of the tri-state gate integrated circuit 3, and the 422T+ port and 422T- port of the physical layer transmitting end 2-2 are respectively connected Connec...
Example Embodiment
[0064] Specific implementation manner two: combination figure 1 with figure 2 To illustrate this embodiment, this embodiment is a further limitation on the full-duplex and half-duplex converter described in Embodiment 1. In this embodiment, the three-state gate integrated circuit 3 includes a first three-state gate 3. -1, the second three-state gate 3-2, the third three-state gate 3-3, the fourth three-state gate 3-4 and the NOT gate 3-5;
[0065] The input terminal of the NOT gate 3-5, the enable signal terminal of the first tri-state gate 3-1, and the enable signal terminal of the second tri-state gate 3-2 are connected together to serve as the tri-state gate integrated circuit 3 The enable signal input terminal, the output terminal of the NOT gate 3-5 is simultaneously connected to the enable signal terminal of the third tri-state gate 3-3 and the enable signal terminal of the fourth tri-state gate 3-4;
[0066] The input of the first tri-state gate 3-1 is connected to the 422T...
Example Embodiment
[0070] Specific implementation mode three: combination figure 1 with image 3 To explain this embodiment, the full-duplex and half-duplex conversion method described in this embodiment is implemented based on the following conversion device: the conversion device includes a half-duplex signal acquisition module 1, a full-duplex data processing module 2 and three The state gate integrated circuit 3, the full-duplex data processing module 2 includes a physical layer receiving end 2-1, a physical layer sending end 2-2, and an FPGA chip 2-3;
[0071] The half-duplex signal acquisition module 1 is implemented using an RS485 chip, and the physical layer receiving end 2-1 and the physical layer transmitting end 2-2 are both implemented using a 422 serial port driver module;
[0072] The 422R+ port and 422R- port of the physical layer receiving end 2-1 are respectively connected to the data signal output + port and data signal output port of the tri-state gate integrated circuit 3, and the...
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