A High Speed, High Precision, Low Offset Fully Differential Dynamic Comparator
A dynamic comparator, high-precision technology, applied in multiple input and output pulse circuits, etc., can solve the problems of low speed and low precision of the comparator, and achieve the effect of improving the operation speed
Active Publication Date: 2016-11-09
XIDIAN UNIV
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Problems solved by technology
[0005] In order to solve the defects of low speed and low precision of existing comparators, the present invention provides a high-speed, high-precision, low-offset fully differential dynamic comparator
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[0025] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.
[0026] Such as figure 1 As shown, it is a circuit diagram of a high-speed, high-precision, low-offset fully differential dynamic comparator according to an embodiment of the present invention, Vin+ and Vin- in the figure are positive and negative input voltage signals, and Vref+ and Vref- are positive and negative input reference voltages signal, Ф clk , Ф clkB is the reset signal (Ф clk with Ф clkB It is an in-phase reset signal, only the potential of the high level is different. where Ф clk The potential of the high level is VDD, Ф clkB The high-level potential is the internal reference potential), and Vout+ and Vout- are positive and negative output voltage signals. The comparator includes: a first transistor M1, a second transistor M2, a third...
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The invention provides a high-speed high-precision low-detuning fully differential dynamic comparator. The dynamic comparator comprises transistors from M1 to M8, transistors from M11 to M16, grid electrodes of the transistor M5, the transistor M6, the transistor M11, the transistor M14, the transistor M15 and the transistor M16 are connected with reset signals, and the dynamic comparator further comprises a transistor M9 and a transistor M10. When the comparator is in a latched state, the electric potential of the node D1 (the combined point of the source electrode of the transistor M7, the drain electrode of the transistor M15 and the drain electrode of the transistor M2 ) and the electric potential of the node D2 (the combined point of the source electrode of the transistor M8, the drain electrode of the transistor M16, the drain electrode of the transistor M1 and the drain electrode of the transistor M3) are pulled up to VDD, and it is ensured that output is not affected when the electric potential of the node D1 and the electric potential of the node D2 are in a comparison state; in addition, the electric potential of the node D1 and the electric potential of the node D2 are pulled up to VDD-Vthn by additionally arranging the transistor M9 and the transistor M10, compared with a traditional comparator, the reset signals are lowered by a threshold voltage, and calculating speed is increased.
Description
technical field [0001] The invention relates to the field of analog circuit design, in particular to a high-speed, high-precision, low-offset fully differential dynamic comparator applied to an analog-to-digital converter without a sample-hold circuit at the front end. Background technique [0002] With the rapid development of wireless communication technology, the demand for devices that use convenient batteries to operate continues to increase, and it is inevitable to develop low-power technology based on high-speed and high-precision application devices. [0003] Reducing the feature size of the process is one of the main ways to reduce power consumption, but it comes with severe process variables and other non-linear influence factors. These problems also limit the performance of high-speed and high-precision analog-to-digital converters. [0004] For non-sample-and-hold ADCs, the power consumption is mainly limited by the interstage gain amplifiers and comparators. T...
Claims
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IPC IPC(8): H03K5/22
Inventor 刘敏杰朱樟明刘术彬杨银堂
Owner XIDIAN UNIV