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Data transmission method and device and direct memory access

A data transmission method and memory technology, applied in the field of direct memory access, data transmission method, and device, can solve the problem of low resource utilization and achieve the effect of improving data transmission efficiency

Inactive Publication Date: 2014-09-03
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Aiming at the relatively low resource utilization rate of DMA for data transmission in the related art, the present invention provides a data transmission method, device and direct memory access to at least solve this problem

Method used

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  • Data transmission method and device and direct memory access
  • Data transmission method and device and direct memory access
  • Data transmission method and device and direct memory access

Examples

Experimental program
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Embodiment 1

[0068] This preferred embodiment provides an improved DMA method for data transmission. According to the characteristics of time separation of different transmission modes, only one transmission channel is used to realize different transmission functions; the DMA physical bus width is designed to be consistent with the data width (for example: the data width between DMA and SM is 64bit, DMA and PM The data width between DMA and DM is 128bit, and the data width between DMA and DM is 256bit), and multi-band FIFO is used to buffer the inconsistency of the source and destination bus widths.

[0069] In this embodiment, the functions executable by the DMA include: command data transfer from SM to PM, data transfer from SM to DM, and data transfer from DM to SM. This DMA can be configured and accessed by the ARM or DSP core.

[0070] Preferably, DMA includes the following:

[0071] (1) Eight 32-bit wide bidirectional synchronous FIFOs are used to buffer the inconsistency of the da...

Embodiment 2

[0083] This preferred embodiment provides a DMA, such as Figure 5 The DMA is shown, and the composition of the DMA is described in detail in this embodiment.

[0084] In order to achieve DM non-aligned address data access, DMAFIFO is divided into 8 groups (bank), each group (bank) is 32bit wide. Figure 6 is a schematic diagram of the realization of a 5×32-bit bidirectional FIFO according to an embodiment of the present invention, such as Figure 6Implementation of each 32bit FIFO shown. The FIFO depth is 5, which is slightly larger than a burst-16 data volume (when the depth is 4, the DMAFIFO size is 32×4×8bit=64×16bit=1024bit). The FIFO can realize two-way transmission, and five 32-bit registers are multiplexed during two-way transmission. The transmission direction is controlled by the dir signal, mem distinguishes between PM and DM, and the dir and mem signals jointly determine the transmission mode (SM2PM, SM2DM, DM2SM). The "_d" suffix in the figure indicates the do...

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Abstract

Disclosed are a data transmission method and apparatus, and DMA. The method comprises: receiving, by using DMA, data of a source end through a first physical bus, the width of the first physical bus being equal to the data width of data of the source end; converting, by using the DMA, the data of the source end into data of a destination end, the data width of data of the destination end being a data width corresponding to the destination end; and sending, by using the DMA, the data of the destination end to the destination end through a second physical bus, the data width of the second physical bus being equal to the data width of the data of the destination end. By means of the present invention, the resource utilization rate of transmitting data by using DMA is improved.

Description

technical field [0001] The present invention relates to the communication field, in particular, to a data transmission method, device and direct memory access (Direct Memory Access, DMA for short). Background technique [0002] The direct memory access controller technology is widely used in processors and System-On-a-Chip (SoC for short) systems. Its function is to realize high-speed data transmission between the I / O interface and the memory. For a Digital Signal Processor (DSP for short), the DMA module, like the processor core, can access DSP external storage resources and internal memory as a Master, so that the SoC memory outside the DSP and the program memory (Program inside the DSP) Memory (referred to as PM for short) and data memory (Data Memory, referred to as DM) can perform fast data transfer without requiring the DSP core to use its internal registers for inefficient data transfer. DMA, like other peripherals, can receive the parameter configuration of the DSP...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28
CPCG06F13/28G06F13/36
Inventor 文博
Owner ZTE CORP
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