System-on-chip chip test method, device and system

Abstract

Provided are a test method, device and system for a system on chip (SoC) chip. The system comprises: an STC (101), a bus (102) and a peripheral interface (103), wherein the STC (101) is connected to each subsystem of the SoC chip through the bus (102); and the STC (101) receiving the start and end addresses of a test vector configured by an off-chip test terminal through the peripheral interface (103), acquiring the test vector according to the start and end addresses, and executing the test vector so as to obtain test results of corresponding subsystems.

Description

technical field [0001] The present invention relates to chip testing technology, in particular to a system on chip (System on Chip, SoC) chip testing method, device and system. Background technique [0002] At present, SoC chip testing is usually performed by running test codes on an embedded processor of the SoC chip. Since the embedded processor needs to be able to handle hundreds of instructions (Command), the structure is very complicated. Therefore, it is required that the test code running on the embedded processor has a high complexity, which makes it very difficult to write the test code. If the test code is written improperly, the test result will be inaccurate, and repeated corrections to the test code will lead to The extension of the test cycle reduces the test efficiency. In particular, with the improvement of the integrated circuit production process, the number of subsystems integrated in the SoC chip is increasing, and the number of complex test codes that ...

AI Technical Summary

Problems solved by technology

Since the embedded processor needs to be able to handle hundreds of instructions (Command), the structure is very complex

Therefore, it is required that the test code running on the embedded processor has a high complexity, which makes it very difficult to write the test code. If the test code is written improperly, the test result will be inaccurate, and repeated corrections to the test code will lead to The extension of the test cycle reduces the test efficiency

In particular, with the improvement of integrated circuit production technology, the number of subsystems integrated by SoC chips is increasing, and the number of complex test codes that need to be written is also increasing, which further reduces the test efficiency.

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